TL16C552AFNR Datasheet, PDF (35/38 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
programming
The serial channel of the ACE is programmed by the control registers: LCR, IER, DLL, DLM, MCR, and FCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written to in any order, the IER should be written to last because it controls
the interrupt enables. Once the serial channel is programmed and operational, these registers can be updated
any time the ACE serial channel is not transmitting or receiving data.
receiver
Serial asynchronous data is input into SIN. The ACE continually searches for a high-to-low transition
from the idle state. When the transition is detected, a counter is reset and counts the 16 × clock to 7 1/2, which
is the center of the start bit. The start bit is valid if SIN is still low. Verifying the start bits prevents the receiver
from assembling a false data character due to a low-going noise spike on the SIN input.
The LCR determines the number of data bits in a character (LCR0 and LCR1). When parity is used, LCR3 and
the polarity of parity LCR4 is needed. Status for the receiver is provided in the LSR. When a full character is
received, including parity and stop bits, the data received indicator in LSR0 is set. The CPU reads the receiver
buffer register, which clears LSR0. If the character is not read prior to a new character transfer from the RSR
to the RBR, the overrun error status indicator is set in LSR1. If there is a parity error, the parity error is set in
LSR2. If a stop bit is not detected, a framing error indicator is set in LSR3.
If the data into SIN is a symmetrical square wave, the center of the data cells occurs within ± 3.125% of the
actual center, providing an error margin of 46.875%. The start bit can begin as much as one 16× clock cycle
prior to being detected.
scratchpad register
The scratch register is an 8-bit read/ write register that has no effect on either channel in the ACE. It is intended
to be used by the programmer to hold data temporarily.
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