TL16C552AFNR Datasheet, PDF (29/38 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
master reset (continued)
Table 10. RESET Effects on Registers and Signals
REGISTER/SIGNAL
Interrupt enable register
Interrupt identification register
Line control register
Modem control register
FIFO control register
Line status register
Modem status register
SOUT
Interrupt (RCVR errors)
Interrupt (receiver data ready)
Interrupt (THRE)
Interrupt (modem status changes)
OUT2
RTS
DTR
OUT1
RESET CONTROL
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Read LSR/Reset
Read RBR/Reset
Read IIR/Write THR/Reset
Read MSR/Reset
Reset
Reset
Reset
Reset
RESET
All bits cleared (0 – 3 forced and 4 – 7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4 – 5 are permanently
cleared.
All bits are cleared.
All bits are cleared (5 – 7 permanently).
All bits are cleared.
All bits are cleared, except bits 5 and 6 are set.
Bits 0 – 3 are cleared, bits 4 – 7 input signal.
High
Low
Low
Low
Low
High
High
High
High
modem control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 20. MCR can be written to
and read from. The RTS and DTR outputs are directly controlled by their control bits in this register. A high input
asserts a low signal (active) at the output terminals. The MCR bits are defined in the following bulleted list.
D Bit 0: When MCR0 is set, the DTR output is forced low. When MCR0 is cleared, the DTR output is forced
high. The DTR output of the serial channel can be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.
D Bit 1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced
high. The RTS output of the serial channel can be input into an inverting line driver to obtain the proper
polarity input at the modem or data set.
D Bit 2: MCR2 has no effect on operation.
D Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.
D Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
SOUT is set to the marking (high) state and the SIN is disconnected. The output of the transmitter shift
register is looped back into the receiver shift register input. The four modem control inputs (CTS, DSR, DCD,
and RI) are disconnected. The modem control outputs (DTR, RTS, OUT1, and OUT2) are internally
connected to the four modem control inputs. The modem control output terminals are forced to their inactive
(high) state on the TL16C552A. In the diagnostic mode, data transmitted is immediately received. This
allows the processor to verify the transmit and receive data paths of the selected serial channel. Interrupt
control is fully operational; however, interrupts are generated by controlling the lower four MCR bits
internally. Interrupts are not generated by activity on the external terminals represented by those four bits.
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