TL16C552AFNR Datasheet, PDF (27/38 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
line status register (LSR)
The LSR is a single register that provides status indicators. The LSR bits shown in Table 9 are described in the
following bulleted list.
D Bit 0: DR is the data ready bit. When set, an incoming character is received and transferred into the receiver
buffer register or in the FIFO. LSR0 is cleared by a CPU read of the data in the receiver buffer register or
in the FIFO.
D Bit 1: OE is the overrun error bit. An OE indicates that data in the receiver buffer register is not read by the
CPU before the next character is transferred into the receiver buffer register overwriting the previous
character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An overrun error
occurs in FIFO mode after the FIFO is full and the next character is completely received. The overrun error
is detected by the CPU on the first LSR read after it happens. The character in the shift register is not
transferred to the FIFO, but it is overwritten.
D Bit 2: PE is the parity error bit. A PE indicates that the received data character does not have the correct
parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error and is cleared when
the CPU reads the contents of the LSR. In FIFO mode, the parity error is associated with a particular
character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.
D Bit 3: FE is the framing error bit. An FE indicates that the received character does not have a valid stop bit.
LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level).
The FE indicator is cleared when the CPU reads the contents of the LSR. In FIFO mode, the framing error
is associated with a particular character in the FIFO. LSR3 reflects the error when the character is at the
top of the FIFO.
D Bit 4: BI is the break interrupt bit. BI is set when the received data input is held in the spacing (low) state
for longer than a full word transmission time (start bit + data bits + parity + stop bits). The BI indicator is
cleared when the CPU reads the contents of the LSR. In FIFO mode, this is associated with a particular
character in the FIFO. LSR4 reflects BI when the break character is at the top of the FIFO. The error is
detected by the CPU when its associated character is at the top of the FIFO during the first LSR read. Only
one zero character is loaded into the FIFO when BI occurs.
LSR1 – LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the
interrupt identification register) when any of the conditions are detected. This interrupt is enabled by setting IER2
in the interrupt enable register.
D Bit 5: THRE is the transmitter holding register empty bit. THRE indicates that the ACE is ready to accept
a new character for transmission. The THRE bit is set when a character is transferred from the transmitter
holding register into the transmitter shift register. LSR5 is cleared by the loading of the transmitter holding
register by the CPU. LSR5 is not cleared by a CPU read of the LSR. In FIFO mode when the transmitter
FIFO is empty, this bit is set. It is cleared when one byte is written to the transmitter FIFO. When the THRE
interrupt is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. If THRE is the interrupt source
indicated in IIR, INTRPT is cleared by a read of the IIR.
D Bit 6: TEMT is the transmitter empty bit. TEMT is set when the transmitter holding register (THR) and the
transmitter shift register are both empty. LSR6 is cleared when a character is loaded into the THR and
remains cleared until the character is transferred out of SOUT. TEMT is not cleared by a CPU read of the
LSR. In FIFO mode, when both the transmitter FIFO and shift register are empty, TEMT is set.
D Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is always cleared in TL16C450 mode. In FIFO mode,
it is set when at least one of the following data errors occurs in the FIFO: parity error, framing error, or break
interrupt indicator. It is cleared when the CPU reads the LSR if there are no subsequent errors in the FIFO.
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