TL16C552AFNR Datasheet, PDF (26/38 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
register 2 line printer control register
The line printer control (LPC) register is a read/write port that controls the PD0 – PD7 direction and drives the
printer control lines. Write operations set or clear these bits, whereas read operations return the state of the last
write operation to this register. The bits in this register are defined in Table 8 and the following bulleted list.
Table 8. LPC Register Bit Description
BIT
DESCRIPTION
0
STB
1
AFD
2
INIT
3
SLIN
4
INT2 EN
5
DIR
6
Reserved 0
7
Reserved 0
D Bit 0: STB is the printer strobe control bit. When STB is set, the STB signal is asserted on the LPT interface.
When STB is cleared, the STB signal is negated.
D Bit 1: AFD is the autofeed control bit. When AFD is set, the AFD signal is asserted on the LPT interface.
When AFD is cleared, the signal is negated.
D Bit 2: INIT is the initialize printer control bit. When INIT is set, the INIT signal is negated. When INIT is
cleared, the INIT signal is asserted on the LPT interface.
D Bit 3: SLIN is the select input control bit. When SLIN is set, the SLIN signal is asserted on the LPT interface.
When SLIN is cleared, the signal is negated.
D Bit 4: INT2 EN is the interrupt request enable control bit. When set, INT2 EN enables interrupts from the
LPT port. When cleared, INT2 EN disables interrupts and places INT2 signal in the high-impedance state.
D Bit 5: DIR is the direction control bit which is only used when PEMD is high. When DIR is set, the output
buffers in the LPD port are disableded to allow data driven from external sources to be read from the LPD
port. When DIR is cleared, the LPD port is in the output mode.
D Bits 6 and 7: These bits are reserved and are always cleared.
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