TL16C552AFNR Datasheet, PDF (10/38 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
parallel port timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Note 16 and Figures 15, 16, and 17)
tsu7
Setup time, data valid before STB ↓
th6
Hold time, data valid after STB ↑
tw6
Pulse duration, STB ↓
td10
Delay time, BUSY ↑ to ACK ↓
td11
Delay time, BUSY ↓ to ACK ↓
tw7
Pulse duration, BUSY ↑
tw8
Pulse duration, ACK ↓
td12
Delay time, BUSY ↑ after STB ↑
td13
Delay time, INT2 ↓ after ACK ↓ (see Note 17)
td14
Delay time, INT2 ↑ after ACK ↑ (see Note 17)
td15
Delay time, INT2 ↑ after ACK ↑ (see Note 17)
td16
Delay time, INT2 ↓ after IOR ↑ (see Note 17)
NOTES: 16. These parameters are not production tested.
17. td13 – td16 are all measured with a 15-pF load.
MIN MAX
1
1
1
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Defined by printer
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22
20
24
25
UNIT
µs
µs
µs
ns
ns
ns
ns
PARAMETER MEASUREMENT INFORMATION
CLK (XTAL1)
tw1
2V
0.8 V
2V
0.8 V
tw2
fclock = 16 MHz MAX
Figure 1. CLK Voltage Waveform
Device Under Test
TL16C552A
2.54 V
680 Ω
82 pF
(see Note A)
NOTE A: This includes scope and jig capacitance.
Figure 2. Output Load Circuit
10
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