TL16C552AFNR Datasheet, PDF (19/38 Pages) Texas Instruments – DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PRINCIPLES OF OPERATION
accessible registers
Using the CPU, the system programmer has access to and control over any of the ACE registers that are
summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
ADDRESS
0
0
0†
1†
1
REGISTER
MNEMONIC
RBR
(read only)
THR
(write only)
DLL
DLM
IER
BIT 7
Data Bit 7
(MSB)
Data
Bit 7
Bit 7
Bit 15
0
BIT 6
Data Bit 6
Data
Bit 6
Bit 6
Bit 14
0
BIT 5
Data Bit 5
Data
Bit 5
Bit 5
Bit 13
0
2
FCR
Receiver
Receiver
Reserved
(write only) trigger (MSB) trigger (LSB)
2
IIR
FIFOs
FIFOs
0
(read only)
enabled‡
enabled‡
3
LCR
(DLAB)
Set
Stick
Divisor latch
break
parity
access bit
4
MCR
0
0
0
5
LSR
Error in
(TEMT)
receiver
FIFO‡
Transmitter
empty
6
MSR
(DCD)
(RI)
Data carrier
Ring
detect
indicator
7
SCR
Bit 7
Bit 6
† _{DLAB = 1}
‡ _{These bits are always 0 when FIFOs are disabled.}
(THRE)
Transmitter
holding
register
empty
(DSR)
Data set
ready
Bit 5
REGISTER BIT NUMBER
BIT 4
BIT 3
Data Bit 4
Data Bit 3
Data
Bit 4
Bit 4
Bit 12
0
Data
Bit 3
Bit 3
Bit 11
(EDSSI) Enable
modem status
interrupt
Reserved
0
DMA
mode select
Interrupt ID
bit 3‡
(EPS)
Even parity
select
Loop
(BI)
Break
interrupt
(PEN)
Parity enable
OUT2 Enable
external
interrupt
(INT0 or INT1)
(FE)
Framing
error
BIT 2
Data Bit 2
Data
Bit 2
Bit 2
Bit 10
(ERLSI)
Enable
receiver line
status
interrupt
Transmitter
FIFO reset
Interrupt ID
bit 2
(STB)
Number of
stop bits
OUT1
(an unused
internal
signal)
(PE)
Parity
error
BIT 1
Data Bit 1
Data
Bit 1
Bit 1
Bit 9
(ETBEI)
Enable
transmitter
holding
register
empty
interrupt
Receiver
FIFO reset
Interrupt ID
bit 1
(WLSB1)
Word length
select bit 1
(RTS)
Request
to send
(OE)
Overrun
error
BIT 0
Data Bit 0
(LSB)
Data
Bit 0
Bit 0
Bit 8
(ERBFI)
Enable
received
data
available
interrupt
FIFO
enable
0 if
interrupt
pending
(WLSB0)
Word length
select bit 0
(DTR)
Data
terminal
ready
(DR)
Data
ready
(CTS)
Clear
to send
Bit 4
(∆ DCD)
Delta data
carrier detect
Bit 3
(TERI)
Trailing edge
ring indicator
Bit 2
(∆ DSR)
Delta data
set ready
Bit 1
(∆ CTS)
Delta clear
clear to send
Bit 0
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