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| DAC8565 Datasheet, PDF (7/46 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference | |||
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DAC8565
www.ti.com
SBAS411A â JUNE 2007 â REVISED NOVEMBER 2007
TIMING REQUIREMENTS(1)(2)
At AVDD = IOVDD= 2.7V to 5.5V and â40°C to +105°C range (unless otherwise noted).
DAC8565
PARAMETER
TEST CONDITIONS
MIN TYP MAX
t1(3) SCLK cycle time
IOVDD = AVDD = 2.7V to 3.6V
40
IOVDD = AVDD = 3.6V to 5.5V
20
t2 SCLK HIGH time
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
20
t3 SCLK LOW time
IOVDD = AVDD = 2.7V to 3.6V
20
IOVDD = AVDD = 3.6V to 5.5V
10
t4 SYNC to SCLK rising edge setup time
IOVDD = AVDD = 2.7V to 3.6V
0
IOVDD = AVDD = 3.6V to 5.5V
0
t5 Data setup time
IOVDD = AVDD = 2.7V to 3.6V
5
IOVDD = AVDD = 3.6V to 5.5V
5
t6 Data hold time
IOVDD = AVDD = 2.7V to 3.6V
4.5
IOVDD = AVDD = 3.6V to 5.5V
4.5
t7 SCLK falling edge to SYNC rising edge
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
0
0
t8 Minimum SYNC HIGH time
IOVDD = AVDD = 2.7V to 3.6V
40
IOVDD = AVDD = 3.6V to 5.5V
20
t9 24th SCLK falling edge to SYNC falling edge
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
130
130
t10
SYNC rising edge to 24th SCLK falling edge
(for successful SYNC interrupt)
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
15
15
t11 ENABLE falling edge to SYNC falling edge
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
15
15
t12 24th SCLK falling edge to ENABLE rising edge
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
10
10
t13 24th SCLK falling edge to LDAC rising edge
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
50
50
t14 LDAC rising edge to ENABLE rising edge
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
10
10
t15 LDAC HIGH time
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
10
t16 RST rising edge to SYNC falling edge
IOVDD = AVDD = 2.7V to 3.6V
35
IOVDD = AVDD = 3.6V to 5.5V
35
t17 RST HIGH time
IOVDD = AVDD = 2.7V to 3.6V
10
IOVDD = AVDD = 3.6V to 5.5V
10
(1) All input signals are specified with tR = tF = 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See the Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at IOVDD = VDD = 3.6V to 5.5V and 25MHz at IOVDD = AVDD = 2.7V to 3.6V.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): DAC8565
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