DAC8565 Datasheet, PDF (28/46 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

DAC8565
SBAS411A – JUNE 2007 – REVISED NOVEMBER 2007
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INPUT SHIFT REGISTER
The input shift register (SR) of the DAC8565 is 24
bits wide, as shown in Table 4. It consists of eight
control bits (DB23 to DB16) and 16 data bits (DB15
to DB0). DB23 and DB22 should always be '0'. LD1
(DB21) and LD0 (DB20) control the updating of each
analog output with the specified 16-bit data value or
power-down command. Bit DB19 must always be '0'.
The DAC channel select bits (DB18, DB17) control
the destination of the data (or power-down command)
from DAC A to DAC D. The final control bit, PD0
(DB16), selects the power-down mode of the
DAC8565 channels.
The DAC8565 also supports a number of different
load commands. The load commands are
summarized as follows:
DB21 = 0 and DB20 = 0: Single-channel store. The
temporary register (data buffer) corresponding to a
DAC selected by DB18 and DB17 updates with the
contents of SR data (or power-down).
DB21 = 0 and DB20 = 1: Single-channel update.
The temporary register and DAC register
corresponding to a DAC selected by DB18 and DB17
are updated with the contents of SR data (or
power-down).
DB21 = 1 and DB20 = 0: Simultaneous update. A
channel selected by DB18 and DB17 updates with
the SR data; simultaneously, all the other channels
update with previously stored data (or power-down)
from temporary registers.
DB21 = 1 and DB20 = 1: Broadcast update. If
DB18 = 0, then SR data are ignored and all channels
are updated with previously stored data (or
power-down). If DB18 = 1, then SR data (or
power-down) updates all channels. Refer to Table 5
for more information.
DB23
0
0
LD1 LD0
DB11
D11 D10 D9
D8
Table 4. DAC8565 Data Input Register Format
0
DAC Select 1
DAC Select 0
PD0
D15
D7
D6
D5
D4
D3
DB12
D14
D13
D12
DB0
D2
D1
D0
DB23
0
X
X
X
DB22
0
DB21
LD 1
0
0
0
0
DB20
LD 0
0
0
0
0
DB19
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
X
1
1
0
X
1
1
0
X
1
1
0
Table 5. Control Matrix for the DAC8565
DB18
DAC Sel 1
0
0
1
1
DB17
DAC Sel 0
0
1
0
1
(00, 01, 10, or 11)
(00, 01, 10, or 11)
(00, 01, 10, or 11)
(00, 01, 10, or 11)
(00, 01, 10, or 11)
Broadcast Modes
0
X
1
X
1
X
DB16
PD0
0
0
0
0
1
0
1
0
1
DB15
MSB
DB14
DB13-DB0
MSB-1 MSB-2...LSB
Data
Data
Data
Data
See Table 6
0
Data
See Table 6
0
Data
See Table 6
0
DESCRIPTION
Write to buffer A with data
Write to buffer B with data
Write to buffer C with data
Write to buffer D with data
Write to buffer (selected by DB17 and DB18) with
power-down command
Write to buffer with data and load DAC (selected by
DB17 and DB18)
Write to buffer with power-down command and load
DAC (selected by DB17 and DB18)
Write to buffer with data (selected by DB17 and DB18)
and then load all DACs simultaneously from their
corresponding buffers
Write to buffer with power-down command (selected by
DB17 and DB18) and then load all DACs
simultaneously from their corresponding buffers
X
X
0
Data
1
See Table 6
0
Simultaneously update all channels of DAC8555 with
data stored in each channels temporary register
Write to all channels and load all DACs with SR data
Write to all channels and load all DACs with
power-down command in SR
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