DAC8565 Datasheet, PDF (37/46 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

DAC8565
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MICROPROCESSOR INTERFACING
DAC8565 to an 8051 Interface
Figure 101 shows a serial interface between the
DAC8565 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8565, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051; in this case, port line P3.3 is used. When
data are to be transmitted to the DAC8565, P3.3 is
taken low. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted; then, a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken high following the
completion of the third write cycle. The 8051 outputs
the serial data in a format that has the LSB first. The
DAC8565 requires its data with the MSB as the first
bit received. The 8051 transmit routine must therefore
take this requirement into account, and mirror the
data as needed.
80C51/80L51⁽¹⁾
P3.3
TXD
RXD
NOTE: (1) Additional pins omitted for clarity.
DAC8565⁽¹⁾
SYNC
SCLK
D_IN
Figure 101. DAC8565 to 80C51/80L51 Interface
DAC8565 to Microwire Interface
Figure 102 shows an interface between the DAC8565
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
are clocked into the DAC8565 on the rising edge of
the SK signal.
SBAS411A – JUNE 2007 – REVISED NOVEMBER 2007
Microwire⁽¹⁾
CS
SK
SO
NOTE: (1) Additional pins omitted for clarity.
DAC8565⁽¹⁾
SYNC
SCLK
D_IN
Figure 102. DAC8565 to Microwire Interface
DAC8565 to 68HC11 Interface
Figure 103 shows a serial interface between the
DAC8565 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8565, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal derives from a port line
(PC7), similar to the 8051 diagram.
68HC11⁽¹⁾
PC7
SCK
MOSI
NOTE: (1) Additional pins omitted for clarity.
DAC8565⁽¹⁾
SYNC
SCLK
D_IN
Figure 103. DAC8565 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
low (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8565, PC7 is left low after the first eight bits are
transferred; then, a second and third serial write
operation are performed to the DAC. PC7 is taken
high at the end of this procedure.
Copyright © 2007, Texas Instruments Incorporated
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