DAC8565 Datasheet, PDF (27/46 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

DAC8565
www.ti.com
SERIAL INTERFACE
The DAC8565 has a 3-wire serial interface (SYNC,
SCLK, and D_IN) compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSPs.
See the Serial Write Operation timing diagram for an
example of a typical write sequence.
The write sequence begins by bringing the SYNC line
low. Data from the D_IN line are clocked into the 24-bit
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 50MHz, making
the DAC8565 compatible with high-speed DSPs. On
the 24th falling edge of the serial clock, the last data
bit is clocked into the shift register and the shift
register locks. Further clocking does not change the
shift register data. Once 24 bits are locked into the
shift register, the eight MSBs are used as control bits
and the 16 LSBs are used as data. After receiving the
24th falling clock edge, the DAC8565 decodes the
eight control bits and 16 data bits to perform the
required function, without waiting for a SYNC rising
edge. A new write sequence starts at the next falling
edge of SYNC. A rising edge of SYNC before the
24-bit sequence is complete resets the SPI interface;
no data transfer occurs. After the 24th falling edge of
SCLK is received, the SYNC line may be kept LOW
or brought HIGH. In either case, the minimum delay
time from the 24th falling SCLK edge to the next
falling SYNC edge must be met in order to properly
begin the next cycle. To assure the lowest power
consumption of the device, care should be taken that
the levels are as close to each rail as possible. (Refer
to the Typical Characteristics section for Figure 36,
Figure 57, and Figure 79 (Supply Current vs Logic
Input Voltage).
SBAS411A – JUNE 2007 – REVISED NOVEMBER 2007
IOV_DD AND VOLTAGE TRANSLATORS
The IOV_DD pin powers the the digital input structures
of the DAC8565. For single-supply operation, it can
be tied to AV_DD. For dual-supply operation, the IOV_DD
pin provides interface flexibility with various CMOS
logic families and should be connected to the logic
supply of the system. Analog circuits and internal
logic of the DAC8565 use AV_DD as the supply
voltage. The external logic high inputs translate to
AV_DD by level shifters. These level shifters use the
IOV_DD voltage as a reference to shift the incoming
logic HIGH levels to AV_DD. IOV_DD is ensured to
operate from 2.7V to 5.5V regardless of the AV_DD
voltage, assuring compatibility with various logic
families. Although specified down to 2.7V, IOV_DD
operates at as low as 1.8V with degraded timing and
temperature performance. For lowest power
consumption, logic V_IH levels should be as close as
possible to IOV_DD, and logic V_IL levels should be as
close as possible to GND voltages.
ASYNCHRONOUS RESET
The DAC8565 output is asynchronously set to
zero-scale voltage or mid-scale voltage (depending
on RSTSEL) immediately after the RST pin is brought
low. The RST signal resets all internal registers, and
therefore, behaves like the Power-On Reset. The
RST pin must be brought back to high before a write
sequence starts. If the RSTSEL pin is high, the RST
signal going low resets all outputs to mid-scale. If the
RSTSEL pin is low, the RST signal going low resets
all outputs to zero-scale. RSTSEL should be set at
power-up.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): DAC8565
Submit Documentation Feedback
27