TMS320C6747CZKBT3 Datasheet, PDF (67/227 Pages) Texas Instruments – TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

TMS320C6745, TMS320C6747
www.ti.com
SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013
5.5 Reset
5.5.1 Power-On Reset (POR)
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are tri-stated with the exception of RESETOUT, which remains active
through the reset sequence, and GP7[14]. During reset, GP7[14] is configured as a reserved function, and
its behavior is not deterministic; the user should be aware that this pin will drive a level, and in fact may
toggle, during reset. RESETOUT is an output for use by other controllers in the system that indicates the
device is currently in reset.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For
maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will
always be asserted upon power up and the device's internal emulation logic will always be properly
initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type
of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high
before attempting any emulation or boundary scan operations.
A summary of the effects of Power-On Reset is given below:
• All internal logic (including emulation logic and the PLL logic) is reset to its default state
• Internal memory is not maintained through a POR
• RESETOUT goes active
• All device pins go to a high-impedance state
• The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC.
CAUTION: A watchdog reset triggers a POR.
5.5.2 Warm Reset
A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low
(TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their
default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT, which
remains active through the reset sequence, and GP7[14]. During reset, GP7[14] is configured as a
reserved function, and its behavior is not deterministic; the user should be aware that this pin will drive a
level, and in fact may toggle, during reset. RESETOUT is an output for use by other controllers in the
system that indicates the device is currently in reset.
During emulation, the emulator will maintain TRST high and hence only warm reset (not POR) is available
during emulation debug and development.
A summary of the effects of Warm Reset is given below:
• All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
• Internal memory is maintained through a warm reset
• RESETOUT goes active
• All device pins go to a high-impedance state
Copyright © 2008–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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