TMS320C6747CZKBT3 Datasheet, PDF (203/227 Pages) Texas Instruments – TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

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SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013
5.30 Programmable Real-Time Unit Subsystem (PRUSS)
The Programmable Real-Time Unit Subsystem (PRUSS) consists of
• Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories
• An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
• A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The PRUs can
also work in coordination with the device level host CPU. This is determined by the nature of the program
which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available
between the two PRUs and the device level host CPU.
The PRUs are optimized for performing embedded tasks that require manipulation of packed memory
mapped data structures, handling of system events that have tight realtime constraints and interfacing with
systems external to the device.
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single
64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR)
of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is
documented in Table 5-105 and in Table 5-106. Note that these two memory maps are implemented
inside the PRUSS and are local to the components of the PRUSS.
Table 5-105. Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map
BYTE ADDRESS
0x0000 0000 - 0x0000 0FFF
PRU0
PRU0 Instruction RAM
PRU1
PRU1 Instruction RAM
Table 5-106. Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map
BYTE ADDRESS
0x0000 0000 - 0x0000 01FF
PRU0
Data RAM 0 ⁽¹⁾
PRU1
Data RAM 1 ⁽¹⁾
0x0000 0200 - 0x0000 1FFF
0x0000 2000 - 0x0000 21FF
Reserved
Data RAM 1 ⁽¹⁾
Reserved
Data RAM 0 ⁽¹⁾
0x0000 2200 - 0x0000 3FFF
Reserved
Reserved
0x0000 4000 - 0x0000 6FFF
INTC Registers
INTC Registers
0x0000 7000 - 0x0000 73FF
PRU0 Control Registers
PRU0 Control Registers
0x0000 7400 - 0x0000 77FF
Reserved
Reserved
0x0000 7800 - 0x0000 7BFF
PRU1 Control Registers
PRU1 Control Registers
0x0000 7C00 - 0xFFFF FFFF
Reserved
Reserved
(1) Note that PRU0 accesses Data RAM0 at address 0x0000 0000, also PRU1 accesses Data RAM1 at address 0x0000 0000. Data RAM0
is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for
passing information between PRUs, each PRU can access the data ram of the ‘other’ PRU through address 0x0000 2000.
The global view of the PRUSS internal memories and control ports is documented in Table 5-107. The
offset addresses of each region are implemented inside the PRUSS but the global device memory
mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and
PRU1 can use either the local or global addresses to access their internal memories, but using the local
addresses will provide access time several cycles faster than using the global addresses. This is because
when accessing via the global address the access needs to be routed through the switch fabric outside
PRUSS and back in through the PRUSS slave port.
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Peripheral Information and Electrical Specifications 203
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