TMS320C6747CZKBT3 Datasheet, PDF (1/227 Pages) Texas Instruments – TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

TMS320C6745, TMS320C6747
www.ti.com
SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013
TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor
Check for Samples: TMS320C6745, TMS320C6747
1 TMS320C6745/6747 Fixed/Floating-Point Digital Signal Processor
1.1 Features
123
• Highlights
(EDMA3):
– 375/456-MHz C674x VLIW DSP
– 2 Transfer Controllers
– TMS320C674x Fixed/Floating-Point VLIW
– 32 Independent DMA Channels
DSP Core
– 8 Quick DMA Channels
– Enhanced Direct-Memory-Access Controller
– Programmable Transfer Burst Size
3 (EDMA3)
• TMS320C674x Fixed/Floating-Point VLIW DSP
– 128K-Byte RAM Shared Memory (C6747
Core
Only)
– Load-Store Architecture With Non-Aligned
– Two External Memory Interfaces
Support
– Three Configurable 16550 type UART
– 64 General-Purpose Registers (32 Bit)
Modules
– Six ALU (32-/40-Bit) Functional Units
– LCD Controller (C6747 Only)
• Supports 32-Bit Integer, SP (IEEE Single
– Two Serial Peripheral Interfaces (SPI)
Precision/32-Bit) and DP (IEEE Double
– Multimedia Card (MMC)/Secure Digital (SD)
Precision/64-Bit) Floating Point
– Two Master/Slave Inter-Integrated Circuit
– One Host-Port Interface (HPI) (C6747 only)
– USB 1.1 OHCI (Host) With Integrated PHY
(USB1) (C6747 Only)
• Applications
– Industrial Control
– USB, Networking
– High-Speed Encoding
– Professional Audio
• Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
• 375/456-MHz C674x VLIW DSP
• C674x Instruction Set Features
– Superset of the C67x+™ and C64x+™ ISAs
• Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
• Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal
Approximation (RSQRxP) Operations Per
Cycle
– Two Multiply Functional Units
• Mixed-Precision IEEE Floating Point
Multiply Supported up to:
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
– 2 SP x DP -> DP Every Three Clocks
– 2 DP x DP -> DP Every Four Clocks
• Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
– 3648/2736 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
• C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct-Memory-Access Controller 3
Multiplies, or Eight 8 x 8-Bit Multiplies per
Clock Cycle, and Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
• 128K-Byte RAM Shared Memory (C6747 Only)
• 3.3V LVCMOS IOs (except for USB interfaces)
• Two External Memory Interfaces:
– EMIFA
1
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2
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3
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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