TMS320C6747CZKBT3 Datasheet, PDF (116/227 Pages) Texas Instruments – TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

TMS320C6745, TMS320C6747
SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013
BYTE ADRESS
0x01E2 0000 - 0x01E2 1FFF
Table 5-37. EMAC Control Module RAM
REGISTER DESCRIPTION
EMAC Local Buffer Descriptor Memory
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No.
1 tc(REFCLK)
2 tw(REFCLKH)
3 tw(REFCLKL)
6 tsu(RXD-REFCLK)
7 th(REFCLK-RXD)
8 tsu(CRSDV-REFCLK)
9 th(REFCLK-CRSDV)
10 tsu(RXER-REFCLK)
11 th(REFCLKR-RXER)
Table 5-38. RMII Timing Requirements
PARAMETER
Cycle Time, RMII_MHZ_50_CLK
Pulse Width, RMII_MHZ_50_CLK High
Pulse Width, RMII_MHZ_50_CLK Low
Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High
Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High
Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High
Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High
Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High
Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High
MIN TYP MAX UNIT
20
ns
7
13 ns
7
13 ns
4
ns
2
ns
4
ns
2
ns
4
ns
2
ns
Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter
tolerance of 50 ppm or less.
No.
4 td(REFCLK-TXD)
5 td(REFCLK-TXEN)
Table 5-39. RMII Switching Characteristics
PARAMETER
Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid
Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid
MIN TYP MAX UNIT
2.5
13 ns
2.5
13 ns
1
RMII_MHz_50_CLK
23
5
RMII_TXEN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
RMII_RXER
4
8
5
6
7
9
10
11
Figure 5-30. RMII Timing Diagram
116 Peripheral Information and Electrical Specifications
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