CC2400 Datasheet, PDF (62/84 Pages) Texas Instruments – 2.4 GHz Low-Power RF Transceiver

CC2400
FREQEST (0x07) - Received frequency offset estimation
Bit
15:8
7:0
Field Name
RX_FREQ_OFFSET[7:0]
-
Reset R/W
-
R
0
W0
Description
Estimate of the received signals centre frequency comparison to
the ideal 1 MHz centre frequency. Two's complement signed
value. See page 42.
Reserved, write as 0.
IOCFG (0x08) - I/O configuration register
Bit
15
14:9
Field Name
-
GIO6_CFG[5:0]
Reset R/W
0
W0
11
R/W
8:3
GIO1_CFG[5:0]
60
R/W
2:0
HSSD_SRC[2:0]
0
R/W
Description
Reserved, write as 0.
Configuration of the GIO6 pin. See page 45 for options. The
reset value outputs the signal CRC_OK on pin GIO6.
How to use the GIO1 pin. See page 45 for options. The reset
value outputs the signal LOCK_STATUS on pin GIO1.
For test purposes only.
The HSSD (High Speed Serial Data) test module is used as
follows:
0: Off.
1: Output AGC status (gain setting / peak detector status /
accumulator value)
2: Output ADC I and Q values.
3: Output I/Q after digital down-mixing and channel filtering.
4: Output RX signal magnitude / frequency unfiltered (from
demodulator).
5: Output RX signal magnitude / frequency filtered (from
demodulator).
6: Output RSSI / RX frequency offset estimation
7: Input DAC values.
The HSSD test module requires that the FS is up and running as
it uses CLK_PRE (~150 MHZ) to produce its ~37.5 MHz data
clock and serialize its output words. Also, in order for HSSD to
function properly GRMDM.PIN_MODE must be set for HSSD.
FSMTC (0x0B) - Finite state machine time constants
Bit
15:13
Field Name
TC_RXON2AGCEN[2:0]
Reset R/W
3
R/W
12:10 TC_PAON2SWITCH[2:0]
6
R/W
9:6
RES[9:6]
10
R/W
5:3
TC_TXEND2SWITCH[2:0] 2
R/W
Description
The time in 5 s steps from RX is turned on until the AGC is
enabled. This time constant must be large enough to allow the
RX chain to settle so that the AGC algorithm starts working on a
proper signal. The default value corresponds to 15 us.
The time in s from TX is started until the TX/RX switch allows
the TX signal to pass.
Reserved
The time in s from TX is stopped (for instance the last bit of the
packet is sent) until the RX/TX switch breaks the TX output and
the PKT signal is set.
SWRS042A
Page 62 of 83