CC2400 Datasheet, PDF (22/84 Pages) Texas Instruments – 2.4 GHz Low-Power RF Transceiver

CC2400
t_ps
t_sp
t_ch
t_cl
t_sd
t_hd
t_ns
SCLK:
CSn:
Write to register:
SI
0
A6 A5 A4 A3 A2 A1 A0 X D_W15 D_W14 D_W13 D_W12 D_W11 D_W10 D_W9 D_W8 X D_W7 D_W6 D_W5 D_W4 D_W3 D_W2 D_W1 D_W0
X
SO
S7 S6 S5 S4 S3 S2 S1 S0
X
Read from register:
SI
1 A6 A5 A4 A3 A2 A1 A0
X
SO
S7 S6 S5 S4 S3 S2 S1 S0
D_R15 D_R14 D_R13 D_R12 D_R11 D_R10 D_R9 D_R8
D_R7
D_R6 D_R5 D_R4 D_R3 D_R2 D_R1 D_R0 D_R15
Figure 6. SPI timing diagram
CSn:
Command strobe:
Read or write a whole register (16 bit):
Read or write 8 MSB of a register:
Read or write a whole register continuously:
Read or write n bytes from/to RF FIFO:
ADDR
ADDR
ADDR
ADDR
ADDR_FIFO
DATA_8MSB
DATA_8MSB
DATA_8MSB
DATA_byte0
DATA_8LSB
DATA_8LSB
DATA_byte1
DATA_8MSB
DATA_byte2
DATA_8LSB
DATA_byte3
... DATA_8MSB DATA_8LSB
... DATA_{byte n-2} DATA_{byte n-1}
Figure 7. Configuration registers write and read operations via SPI
Parameter Symbol Min Max Units
Conditions
SCLK, clock
frequency
SCLK low
pulse
duration
SCLK high
pulse
duration
CSn setup
time
CSn hold
time 1
CSn hold
time 2
fSCLK
tcl,min
tch,min
tsp
tns
tps
20
25
25
25
25
300
MHz
ns
ns
ns
ns
ns
SI setup time
tsd
SI hold time
thd
Rise time
trise
25
ns
25
ns
100
ns
Fall time
tfall
100
ns
Note: The set-up- and hold-times refer to 50% of VDD.
The minimum time SCLK must be low.
The minimum time SCLK must be high.
The minimum time CSn must be low before
positive edge of SCLK.
The minimum time CSn must be held low after the
last negative edge of SCLK.
In buffered mode: The minimum time CSn must be
held low after the last positive edge of SCLK. This
only applies to FIFO accesses.
The minimum time data on SI must be ready
before the positive edge of SCLK.
The minimum time data must be held at SI, after
the positive edge of SCLK.
The maximum rise time for SCLK and CSN
The maximum fall time for SCLK and CSn
Table 12. SPI timing specification
SWRS042A
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