CC2400 Datasheet, PDF (46/84 Pages) Texas Instruments – 2.4 GHz Low-Power RF Transceiver

CC2400
10
CARRIER_SENSE_N
O
Carrier sense output (RSSI above threshold)
11
CRC_OK
O
CRC check OK after last byte read from FIFO
12
AGC_EN
O
AGC enable signal
13
FS_PD
O
Frequency synthesiser power down
14
RX_PD
O
RX power down
15
TX_PD
O
TX power down
16
Reserved
O
Reserved
17
Reserved
O
Reserved
18
Reserved
O
Reserved
19
Reserved
O
Reserved
20
Reserved
O
Reserved
21
Reserved
O
Reserved
22
PKT_ACTIVE
O
Packet reception active
23
MDM_TX_DIN
O
The TX data sent to modem
24
MDM_TX_DCLK
O
The TX clock used by modem
26
MDM_RX_DOUT
O
The RX data received by modem
26
MDM_RX_DCLK
O
The RX clock recovered by modem
27
MDM_RX_BIT_RAW
O
The un-synchronized RX data received by modem
28
Reserved
O
Reserved
29
MDM_BACKEND_EN
O
The Backend enable signal used by modem in RX
30
MDM_DEC_OVRFLW
O
Modem decimation overflow
31
AGC_CHANGE
O
Signal that toggles whenever AGC changes gain.
32
VGA_RESET_N
O
The VGA peak detectors' reset signal
33
CAL_RUNNING
O
VCO calibration in progress
34
SETTLING_RUNNING
O
Stepping CHP current after calibration
35
RXBPF_CAL_RUNNING
O
RX band-pass filter calibration running
36
VCO_CAL_START
O
VCO calibration start signal
37
RXBPF_CAL_START
O
RX band-pass filter start signal
38
FIFO_EMPTY
O
FIFO empty signal
39
FIFO_FULL
O
FIFO full signal
40
CLKEN_FS_DIG
O
Clock enable Frequency Synthesiser
41
CLKEN_RXBPF_CAL
O
Clock enable RX band-pass filter calibration
42
CLKEN_GR
O
Clock enable generic radio
43
XOSC16M_STABLE
O
Indicates that the Main crystal oscillator is stable
44
XOSC_16M_EN
O
16 MHz XOSC enable signal
45
XOSC_16M
O
16 MHz XOSC output from analog part
46
CLK_16M
O
16 MHz clock from main clock tree
47
CLK_16M_MOD
O
16 MHz modulator clock tree
48
CLK_8M16M_FSDIG
O
8/16 MHz clock tree for fs_dig module
49
CLK_8M
O
8 MHz clock tree derived from XOSC_16M
50
CLK_8M_DEMOD_AGC
O
8 MHz clock tree for demodulator/AGC
51
Reserved
O
Reserved
52
Reserved
O
Reserved
53
FREF
O
Reference clock (4 MHz)
54
FPLL
O
Output clock of A/M-counter (4 MHz)
55
PD_F_COMP
O
Phase detector comparator output
56
WINDOW
O
Window signal to PD (Phase Detector)
57
LOCK_INSTANT
O
Window signal latched in PD (Phase Detector) by the
FREF clock
58
RESET_N_SYSTEM
O
Chip wide reset (except registers)
59
FIFO_FLUSH
O
FIFO flush signal
60
LOCK_STATUS
O
The top-level FS in lock status signal
61
ZERO
O
Output logic zero
62
ONE
O
Output logic one
63
HIGH_Z
-
Pin set as high-impedance output
Table 18. GIO1 / GIO6 signal select table
SWRS042A
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