TLC5911 Datasheet, PDF (6/30 Pages) Texas Instruments – LED DRIVER

TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
Terminal Functions (Continued)
TERMINAL
NAME
NO.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{DIN0 – DIN9}
76,77,78,79,80,
81,82,83,84,85
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{DOUT0 – DOUT9}
41,42,43,44,45,
46,47,48,49,50
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DPOL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GNDANA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GNDLOG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GNDLED
96
28
98
1,4,7,10,13,
16,19,22,25
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GSCLK
68
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GSPOL
69
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _IREF
32
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _LEDCHK
58
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{MAG0 – MAG2}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _NC
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{OUT0 – DOUT15}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _PDOUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RBIAS
73,72,71
57
2,3,5,6,8,9,11,
12,14,15,17,18,
20,21,23,24
70
74
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RSEL0
60
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RSEL1
59
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TEST1 – TEST3
THERMAL PAD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _TSENA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VCCANA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VCCLOG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VCCLED
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VCOIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^WDCAP
97,99,100
Package bottom
31
33
93
26
75
30
I/O
DESCRIPTION
Input for 10 bit parallel data (port A). These terminals are inputs for shift register for gray
I scale data, brightness control, and dot correction data. The register selected is determined
by RSEL0, 1.
Output for 10 bit parallel data (port A). These terminals are outputs for shift register for gray
O scale data, brightness control, and dot correction data. The register selected is determined
by RSEL0, 1.
I
Selects the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When
DPOL is low, the falling edge of DCLK is valid.
Analog ground (Internally connected to GNDLOG and GNDLED)
Logic ground (Internally connected to GNDANA and GNDLED)
LED driver ground (Internally connected to GNDANA and GNDLED)
Clock input for gray scale. When MAG0 through MAG2 are all low, GSCLK is used for pulse
I
width control. When MAG0 through MAG2 are not low, GSCLK is used for PLL timing control.
The gray scale display is accomplished by lighting the LED until the number of GSCLK or
PLL clocks counted is equal to the data latched.
Select the valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid.
I _{When GSPOL is low, the falling edge of GSCLK is valid.}
Constant current value setting. LED current is set to the desired value by connecting an
I/O external resistor between IREF and GND. The 38 times current is compared to current
across the external resistor sink on the output terminal.
LED disconnection detection enable. When LEDCHK is high, the LED disconnection
I detection is enabled and XDOWN2 is valid. When LEDCHK is low, the LED disconnection
detection is disabled.
I
PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is
set .
No internal connection
O Constant current output
I/O Resistor connection for PLL feedback adjustment
I/O Resistor connection for PLL oscillation frequency setting
Input/output port selection and shift register data latch switching.
When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected to
port A, and the dot correction register latch is selected to port B.
I When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to
port A, and the dot correction register latch is selected to port B.
When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port A
and no register latch is selected to port B.
I TEST. Factory test terminal. These terminals should be connected to GND.
Heat sink pad. This pad is connected to the lowest potential IC or thermal layer.
I TSD enable. When TSENA is high, TSD is enabled. When TSENA is low, TSD is disabled.
Analog power supply voltage
Logic power supply voltage
LED driver power supply voltage
I/O Capacitance connection for PLL feedback adjustment
WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor
I/O between WDCAP and GND. When WDCAP is directly connected to GND, the WDT function
is disabled. In this case, WDTRG should be tied to high or low level.
6
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