TLC5911 Datasheet, PDF (13/30 Pages) Texas Instruments – LED DRIVER

PRINCIPLES OF OPERATION
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
setting for output constant current value
On the constant current output terminals (OUT0–15), approximately 38 times the current which flows through
the external resistor, R_(IREF) (connected between IREF and GND), can flow. The external resistor value is
calculated using the following equation:
R_(IREF) (Ω) ≅ 38 × 1.2 (V) / I_OL(C)(A) where both BCENA and DCENA are low.
Note that more current flows if IREF is connected to GND directly.
constant output current operation
The constant current output turns on (sink constant current), if GSPOL is high and if all the gray scale data
latched into the gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge
of the gray scale clock when BLANK goes from high to low. After that, the number of the falling edge is counted
by the 10-bit gray scale counter. Then, the output counted corresponding to the gray scale data is turned off
(stop to sink constant current). The gray scale clock can be selected, as discussed in later section, from GSCLK
or by internal PLL circuitry. If the shift register for the gray scale is updated during XLATCH high, the data on
the gray scale data latch is also updated affecting the number of the gray scale of constant current output.
Accordingly, during the on-state of the constant current output, XLATCH should be kept at a low level and the
gray scale data latch should be held.
input/output port and shift register selection
The TLC5911 supplies two parallel input ports such as DIN (10 bits : port A) and DCDIN (7 bits: port B). The
DIN and DCDIN ports also supply DCLK and DCCLK for the shift clock, XLATCH and XDCLAT for latch, and
DOUT and DCDOUT for output, respectively. The device has three kinds of shift register latchs such as the gray
scale data, brightness control, and dot correction. The port and shift registers can be selected by RSEL0 and
RSEL1. The selection of the shift registers will be done by RESL0 and RSEL1 as shown in Table 1. Note that
the RSELn setting is done at DCLK low and DPOL high (DCLK is high when DPOL is low). When only port A
is used, DCDIN, DCDOUT, DCCLK, and XDCLAT should be connected to GND.
Table 1. Shift Register Latch Selection
SELECTED SHIFT REGISTER LATCH
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PORT A}
PORT B
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{RSEL1 RSEL0 DIN, DCLK, XLATCH, DOUT DCDIN, DCCLK, XDCLAT}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _L
L
Gray scale data displayed
Dot correction
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _L
H
Brightness control
Dot correction
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _H
L
Dot correction (see Note 4)
Not connected
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _H
H
N/A (inhibit)
N/A (inhibit)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{NOTE 4: Zero is output to DOUT7 through DOUT9.}
DCDOUT
Dot correction
Dot correction
Dot correction
N/A (inhibit)
shift register latch for gray scale data
The shift register latch for the gray scale data is configured with 16 × 10 bits. The gray scale data, configured
with 10 bits, represents the time when constant current output is being turned on, and the data range is 0 to 1023
(00h to 3FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on (light off). On
the other hand, when the gray scale data is 1023, the time is longest, and it turns on during the time of the 1023
clocks from the gray scale clock. The configuration of the shift register and the latch for gray scale data is shown
in Figure 3.
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