TLC5911 Datasheet, PDF (5/30 Pages) Texas Instruments – LED DRIVER

TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
equivalent input and output schematic diagrams
Input
VCCIF
DOUT0–9, DCDOUT0–6, XGSOUT, XPOUT, BOUT
VCCLOG
OUTPUT
INPUT
GNDLOG
GNDLOG
XDOWN1, XDOWN2
XDOWN1, XDOWN2
OUTn
OUTn
GNDLOG
GNDLED
Terminal Functions
TERMINAL
NAME
NO.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _BCENA
94
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _BLANK
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _BOUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DCCLK
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DCDIN0 –
DCDIN6
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{DCDOUT0 –}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DCDOUT6
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DCENA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DCLK
67
53
62
86,87,88,
89,90,91,92
34,35,36,
37,38,39,40
95
64
I/O
DESCRIPTION
Brightness control enable. When BCENA is low, the brightness control latch is set to the
I
default value. The output current value in this status is 100% of the value set by an external
resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high, writing to
brightness control latch is enabled.
Blank (Light off). When BLANK is high, all output of the constant current driver are turned
off. When GSPOL is high, all the output is turned on (LED on) synchronizing to the falling
I edge of GCLK after next rising edge of GSCLK when BLANK goes from high to low. When
GSPOL is low, all the output is turned on (LED on) synchronizing to the rising edge of GCLK
after next falling edge of GSCLK when BLANK goes from high to low.
O BLANK buffered output
Clock input for data transfer. The input data is from DCDIN (port B) . The output data at
I DCDOUT. All data on the shift register for dot correction data from DCDIN is shifted by 1 bit
and is synchronized to the rising edge of DCCLK.
I
Input for 7 bit parallel data (port B). These terminals are used as shift register input for dot
correction data.
Output for 7 bit parallel data (port B). These terminals are used as shift register output for
O _{dot correction data.}
I
Latch enable for dot correction data. When DCENA is low, the latch is set to the default value.
At this time, the output current value is 100% of the value set by an external resistor.
Clock input for data transfer. The input data is from DIN (port A) , all the data on the shift
I
register selected by RSEL0, 1 and the output data at DOUT are shifted by 1 bit and
synchronized to DCLK. Note that whether synchronizing to the rising or falling edge of DCLK
is dependent on the value of DPOL.
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