TLC5911 Datasheet, PDF (15/30 Pages) Texas Instruments – LED DRIVER

XDCLAT
PRINCIPLES OF OPERATION
Latch for Dot Correction
OUT15
Data
(7 bits)
OUT14
Data
(7 bits)
OUT1
Data
(7 bits)
TLC5911
LED DRIVER
SLLS402 – DECEMBER 1999
OUT0
Data
(7 bits)
DCDOUT0 to 6
Shift Register for Dot Correction
16th byte
DCDIN6 MSB
DCDIN0 LSB
15th byte
DCDIN6 MSB
DCDIN0 LSB
2nd byte
DCDIN6 MSB
DCDIN0 LSB
1st byte
DCDIN6 MSB
DCDIN0 LSB
XLATCH
Using Port B (RSEL0=L or H, RSEL1=L)
Latch for Dot Correction
OUT15
Data
(7 bits)
OUT14
Data
(7 bits)
OUT1
Data
(7 bits)
OUT0
Data
(7 bits)
DCCLK
DCDIN0 to 6
DOUT0 to 6
Shift Register for Dot Correction
16th byte
DIN6 MSB
DIN0 LSB
15th byte
DIN6 MSB
DIN0 LSB
2nd byte
DIN6 MSB
DIN0 LSB
1st byte
DIN6 MSB
DIN0 LSB
DCLK
DIN0 to 6
Using Port A (RSEL0=L, RSEL1=H)
Figure 5. Relationship Between the Shift Register and the Latch for Dot Correction
write data to shift register latch
The shift register latch written is selected using the RSEL0 and RSEL1 terminal. At port A, the data is applied
to the DIN data input terminal, clocked into the shift register and synchronized to the rising edge of DCLK after
XENABLE is pulled low. At port B, the data is applied to the DCDIN data input terminal, clocked into the shift
register, and synchronized to the rising edge of DCCLK. The shift register for the gray scale data is configured
with 16 × 10 bits and the shift register for dot correction is configured with 16 × 7 bits resulting in sixteen times
DCLK. The shift register for the brightness control is configured with 1 × 10 bits resulting in one times DCLK.
At the number of DCLK input for each case, data can be written into the shift register. In this condition, when
the XLATCH at port A or the XDCLAT at port B is pulled high, data in the shift register is clocked into the latch
(data through). When the XLATCH at port A or XDCLAT at port B is pulled low, data is held (latch).
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