TLC5911 Datasheet, PDF (17/30 Pages) Texas Instruments – LED DRIVER

TLC5911
LED DRIVER
PRINCIPLES OF OPERATION
SLLS402 – DECEMBER 1999
output current adjustment on each constant current output – LED brightness adjustment
By using the dot correction latch, the output current on each constant current output can be adjusted in 128 steps
as 1 step of 0.8% of the current ratio between 100% and 0% when the output current is set to 100% of an external
resistor at 7Fh of the latched value and the lower 6 bits of the brightness control register. By using this function,
the brightness deviation from the LED brightness variation can be minimized. When DCENA is pulled low, the
output current is set to 100% without the dot correction.
Table 4. Relative Current Ratio By Constant Current Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _CODE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MSB 0000000 LSB
.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _.
.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _1111110
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _1111111†
CURRENT RATIO %
0.0
.
.
.
.
99.2
100
IOL(C)=40 (mA)
0.0
.
.
.
.
39.7
40
† _{DCENA is low.}
clock edge selection
The high speed clock signal is diminished due to the duty ratio change through the multiple stages of the IC or
module as shown in Figure 6.
IN
A
OUT
IN
A
A’
OUT
OUT’
IN
A
OUT
IN’
A’
OUT
a) Propagate through multiple stages buffer
with slow falling edge
b) Insert inverter between buffers
Figure 6. Clock Edge Selection
In Figure 6a, if the falling edge at the internal buffer is behind the rising edge, the clock will disappear if a multiple
cascade connection is made. To resolve this problem, the duty ratio can be held unchanged using the
connection as shown in Figure 6b if the valid clock edge can be selected (arrow in Figure 6). Note that the clock
delay is not avoided even in this case.
The device incorporates the clock edge selection function for each DCLK and GSCLK. By using this function,
the falling edge or rising edge for the valid edge can be selected depending on the status of DPOL and GSPOL,
thus the degradation for the duty ratio can be reduced. The relationship between each signal is shown in Table 5.
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