TLC32040C Datasheet, PDF (6/33 Pages) Texas Instruments – ANALOG INTERFACE CIRCUITS

TLC32040C, TLC32040I, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995
detailed description
analog input
Two sets of analog inputs are provided. Normally, the IN + and IN – input set is used; however, the auxiliary input
set, AUX IN + and AUX IN – , can be used if a second input is required. Each input set can be operated in either
differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain
for the IN +, IN –, AUX IN +, and AUX IN – inputs can be programmed to be either 1, 2, or 4 (see Table 2). Either
input circuit can be selected via software control. It is important to note that a wide dynamic range is assured
by the differential internal analog architecture and by the separate analog and digital voltage supplies and
grounds.
A/D bandpass filter, A/D bandpass filter clocking, and A/D conversion timing
The A/D bandpass filter can be selected or bypassed via software control. The frequency response of this filter
is presented in the following pages. This response results when the switched-capacitor filter clock frequency
is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the
filter clock frequency is not 288 kHz, the filter transfer function is frequency scaled by the ratio of the actual clock
frequency to 288 kHz. The low-frequency roll-off of the high-pass section is 300 Hz.
The internal timing configuration and AIC DX data word format sections of this data sheet indicate the many
options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate that the RX
counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock for several master
clock input frequencies.
The A/D conversion rate is then attained by frequency dividing the 288-kHz bandpass switched-capacitor filter
clock with the RX counter B. Thus, unwanted aliasing is prevented because the A/D conversion rate is an
integral submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are
synchronously locked.
A/D converter performance specifications
Fundamental performance specifications for the A/D converter circuitry are presented in the A/D converter
operating characteristics section of this data sheet. The realization of the A/D converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold.
analog output
The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier outputs
are brought out of this integrated circuit. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.
D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing
The frequency response of this filter is presented in the following pages. This response results when the
low-pass switched-capacitor filter clock frequency is 288 kHz. Like the A/D filter, the transfer function of this filter
is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output
on the output of the D/A low-pass filter to greatly attenuate any switched-capacitor clock feedthrough.
The D/A conversion rate is then attained by frequency dividing the 288-kHz switched-capacitor filter clock with
TX counter B. Thus, unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple
of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.
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