TLC32040C Datasheet, PDF (11/33 Pages) Texas Instruments – ANALOG INTERFACE CIRCUITS

TLC32040C, TLC32040I, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
AIC DR or DX word bit pattern
A/D or D/A MSB,
1st bit sent
1st bit sent of 2nd byte
SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995
A/D or D/A LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
AIC DX data word format section
d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 COMMENTS
primary DX serial communication protocol
←d15 (MSB) through d2 go to the D/A
converter register
→ 0 0 The TX and RX counter As are loaded with the TA
and RA register values. The TX and RX counter Bs
are loaded with TB and RB register values.
←d15 (MSB) through d2 go to the D/A
converter register
→ 0 1 The TX and RX counter As are loaded with the TA +
TA’ and RA + RA’ register values. The TX and RX
counter Bs are loaded with TB and RB register
values. Bits d1 = 0 and d0 =1 cause the next D/A and
A/D conversion periods to be changed by the
addition of TA’ and RA’ master clock cycles, in which
TA’ and R/A’ can be positive or negative or zero (refer
to Table 1).
←d15 (MSB) through d2 go to the D/A
converter register
→ 1 0 The TX and RX counter As are loaded with the TA –
TA’ and RA – RA’ register values. The TX and RX
counter Bs are loaded with TB and RB register
values. Bits d1 = 1 and d0 = 0 cause the next D/A and
A/D conversion periods to be changed by the
subtraction of TA’ and RA’ master clock cycles, in
which TA’ and R/A’ can be positive or negative or zero
(refer to Table 1).
←d15 (MSB) through d2 go to the D/A
converter register
→ 1 1 The TX and RX counter As are loaded with the TA
and RA register values. The TX and RX counter Bs
are loaded with the TB and RB register values. After
a delay of four shift clock cycles, a secondary
transmission immediately follows to program the AIC
to operate in the desired configuration.
NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (primary communications) to the AIC initiates
secondary communications upon completion of the primary communications.
Upon completion of the primary communication, FSX remains high for four SHIFT CLK cycles and then goes low and initiates the
secondary communication. The timing specifications for the primary and secondary communications are identical. In this manner, the
secondary communication, if initiated, is interleaved between successive primary communications. This interleaving prevents the
secondary communication from interfering with the primary communications and DAC timing, thus preventing the AIC from skipping a DAC
output. In the synchronous mode, FSR is not asserted during secondary communications.
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