TLC32040C Datasheet, PDF (23/33 Pages) Texas Instruments – ANALOG INTERFACE CIRCUITS

TLC32040C, TLC32040I, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995
timing requirements
serial port recommended input signals
tc(MCLK)
tr(MCLK)
tf(MCLK)
tsu(DX)
th(DX)
Master clock cycle time
Master clock rise time
Master clock fall time
Master clock duty cycle
RESET pulse duration (see Note 12)
DX setup time before SCLK↓
DX hold time after SCLK↓
MIN
95
42%
800
20
tc(SCLK)/4
MAX
10
10
58%
UNIT
ns
ns
ns
ns
ns
ns
serial port – AIC output signals, C_L = 30 pF for SHIFT CLK output, C_L = 15 pF for all other outputs
MIN TYP† MAX UNIT
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
380
ns
3
8 ns
3
8 ns
45
55 %
td(CH-FL) Delay from SCLK↑ to FSR / FSX / FSD↓
30
ns
td(CH-FH) Delay from SCLK↑ to FSR / FSX / FSD↑
35
90 ns
td(CH-DR) DR valid after SCLK↑
90 ns
td(CH-EL) Delay from SCLK↑ to EODX / EODR↓ in word mode
90 ns
td(CH-EH) Delay from SCLK↑ to EODX / EODR↑ in word mode
90 ns
tf(EODX) EODX fall time
2
8 ns
tf(EODR) EODR fall time
2
8 ns
td(CH-EL) Delay from SCLK↑ to EODX / EODR↓ in byte mode
90 ns
td(CH-EH) Delay from SCLK↑ to EODX / EODR↑ in byte mode
90 ns
td(MH-SL) Delay from MSTR CLK↑ to SCLK↓
65 170 ns
td(MH-SH) Delay from MSTR CLK↑ to SCLK↑
65 170 ns
† _{Typical values are at TA = 25°C.}
NOTE 12: RESET pulse duration is the amount of time that the reset terminal is held below 0.8 V after the power supplies have reached their
recommended values.
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