TLC32040C Datasheet, PDF (3/33 Pages) Texas Instruments – ANALOG INTERFACE CIRCUITS

functional block diagram
TLC32040C, TLC32040I, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995
IN +
IN –
AUX IN +
AUX IN –
OUT +
OUT –
Band-Pass Filter
M
U
X
M
U
X
Low-Pass Filter
Transmit Section
A/D
Internal
Voltage
Reference
(TLC32040
only)
D/A
Serial
Port
FSR
DR
EODR
MSTR CLK
SHIFT CLK
WORD/BYTE
DX
FSX
EODX
VCC ₊ VCC _– ANLG DTGL VDD
GND GND (DIGITAL)
REF
RESET
TERMINAL
NAME
NO.
ANLG GND
17,18
AUX IN +
24
AUX IN –
23
DGTL GND
9
DR
5
DX
12
EODR
3
Terminal Functions
I/O
DESCRIPTION
Analog ground return for all internal analog circuits. Not internally connected to DGTL GND.
I Noninverting auxiliary analog input state. This input can be switched into the bandpass filter and A/D
converter path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs
replace the IN + and IN – inputs. If the bit is a 0, the IN + and IN – inputs are used (see the AIC DX data word
format section).
I Inverting auxiliary analog input (see the above AUX IN + description)
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
O DR is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission of bits
from the AIC to the TMS320 serial port is synchronized with the SHIFT CLK signal.
I DX is used to receive the DAC input bits and timing and control information from the TMS320. This serial
transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT CLK signal.
O End of data receive. See the WORD/BYTE description and the Serial Port Timing diagrams. During the
word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of A/D information
have been transmitted from the AIC to the TMS320 serial port. EODR can be used to interrupt a
microprocessor upon completion of serial communications. Also, EODR can be used to strobe and enable
external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus
communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing,
EODR goes low after the first byte has been transmitted from the AIC to the TMS320 serial port and is kept
low until the second byte has been transmitted. The TMS32011 or TMS320C17 can use this low-going
signal to differentiate between the two bytes as to which is first and which is second. EODR does not occur
after secondary communication.
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