TLC32040C Datasheet, PDF (12/33 Pages) Texas Instruments – ANALOG INTERFACE CIRCUITS

TLC32040C, TLC32040I, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995
secondary DX serial communication protocol
x x | ← to TA register → | x x | ← to RA register → |
x | ← to TA’ register → | x | ← to RA’ register → |
x | ← to TB register → | x | ← to RB register → |
x x x x x x x x d7 d6 d5 d4 d3 d2
Control
register
0 0 d13 and d6 are MSBs (unsigned binary)
0 1 d14 and d7 are 2’s complement sign bits
1 0 d14 and d7 are MSBs (unsigned binary)
11
d2 = 0/1 deletes/inserts the bandpass filter
d3 = 0/1 disables/enables the loopback function
d4 = 0/1 disables/enables the AUX IN + and AUX IN – terminals
d5 = 0/1 asynchronous/synchronous transmit receive sections
d6 = 0/1 gain control bits (see gain control section)
d7 = 0/1 gain control bits (see gain control section)
reset function
A reset function is provided to initiate serial communications between the AIC and DSP. The reset function
initializes all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on RESET initializes the AIC registers to provide an 8-kHz A/D and D/A conversion rate
for a 5.184-MHz master clock input signal. The AIC, except the control register, is initialized as follows (see AIC
DX data word format section):
REGISTER
TA
TA’
TB
RA
RA’
RB
INITIALIZED
REGISTER
VALUE (HEX)
9
1
24
9
1
24
The control register bits are reset as follows (see AIC DX data word format section):
d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1
This initialization allows normal serial port communications to occur between AIC and DSP. If the transmit and
receive sections are configured to operate synchronously and the user wishes to program different conversion
rates, only the TA, TA’, and TB register need to be programmed, since both transmit and receive timing are
synchronously derived from these registers (see the terminal descriptions and AIC DX word format sections).
The circuit shown below provides a reset on power up when power is applied in the sequence given under
power-up sequence. The circuit depends on the power supplies reaching their recommended values a minimum
of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
TLC32040/
TLC32041
VCC ₊
RESET
VCC _–
5V
200 kΩ
0.5 µF
–5 V
12
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