TLC32040C Datasheet, PDF (20/33 Pages) Texas Instruments – ANALOG INTERFACE CIRCUITS

TLC32040C, TLC32040I, TLC32041C, TLC32041I
ANALOG INTERFACE CIRCUITS
SLAS014E – SEPTEMBER 1987 – REVISED MAY 1995
electrical characteristics over recommended operating free-air temperature range, V_CC+ = 5 V,
V_CC– = –5 V, V_DD = 5 V (unless otherwise noted)
total device, MSTR CLK frequency = 5.184 MHz, outputs not loaded
PARAMETER
TEST CONDITIONS
VOH High-level output voltage
VOL Low-level output voltage
ICC ₊ Supply current from VCC ₊
TLC3204_C
TLC3204_I
VDD = 4.75 V, IOH = – 300 µA
VDD = 4.75 V, IOL = 2 mA
ICC _– Supply current from VCC _–
TLC3204_C
TLC3204_I
IDD
Vref
∝_Vref
ro
Supply current from VDD
Internal reference output voltage
Temperature coefficient of internal reference voltage
Output resistance at REF
fMSTR _CLK = 5.184 MHz
MIN TYP†
2.4
3
200
100
MAX UNIT
V
0.4 V
35
mA
40
– 35
mA
– 40
7 mA
3.3 V
ppm/°C
kΩ
receive amplifier input
PARAMETER
A/D converter offset error (filters bypassed)
A/D converter offset error (filters in)
CMRR
Common-mode rejection ratio at IN +, IN –, or AUX IN +,
AUX IN –
rl
Input resistance at IN +, IN –, or AUX IN +,AUX IN –, REF
TEST CONDITIONS
See Note 6
MIN TYP†
25
25
MAX
65
65
UNIT
mV
mV
55
dB
100
kΩ
transmit filter output
PARAMETER
VOO
Output offset voltage at OUT +, OUT –, (single-ended
relative to ANLG GND)
VOM
Maximum peak output voltage swing across RL at OUT +
or OUT –, (single ended)
VOM
Maximum peak output voltage swing between RL at OUT +
and OUT –, (differential output)
TEST CONDITIONS
RL ≥ 300 Ω, Offset voltage = 0
RL ≥ 600 Ω
MIN TYP† MAX UNIT
15
75 mV
±3
V
±6
V
system distortion specifications, SCF clock frequency = 288 kHz
PARAMETER
TEST CONDITIONS
MIN TYP† MAX UNIT
Attenuation of second harmonic of A/D
Single ended _{VI = – 0.5 dB to – 24 dB referred to Vref,}
70
dB
input signal
Differential
See Note 7
62
70
Attenuation of third and higher harmonics ^{Single ended} VI = – 0.5 dB to – 24 dB referred to Vref,
65
dB
of A/D input signal
Differential
See Note 7
57
65
Attenuation of second harmonic of D/A
Single ended _{VI = – 0 dB to – 24 dB referred to Vref,}
70
dB
input signal
Differential
See Note 7
62
70
Attenuation of third and higher harmonics
of D/A input signal
Single ended
Differential
VI = – 0 dB to – 24 dB referred to Vref,
See Note 7
65
57
65
dB
† _{All typical values are at TA = 25°C.}
NOTES: 6. The test condition is a 0-dBm, 1-kHz input signal with an 8-kHz conversion rate.
7. The test condition VI is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC
is 600 Ω.
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