GC3011 Datasheet, PDF (6/35 Pages) Texas Instruments – DIGITAL RESAMPLER

GC3011 DIGITAL RESAMPLER
2.6 MULTI-CHIP SYNC AND OFFSET CIRCUIT
The multi-chip sync and offset circuit allows multiple chips to be used in parallel, all locked to the
same resampling ratio and phase. The circuit also allows each chip to be offset by a fixed time delay relative
to the others. A block diagram of the circuit is shown in Figure 3.
DC[0:11]
CV
FIZ FOZ
M/S
BI-DIR CONTROL
NOTE: FOZ and FIZ go to the FIFO
From
Delay
Accumulator
Delay Control
Valid
Multi-chip
Mode
Delay
Offset
OFFSET
Delay Control
Control Valid
14 bits
Figure 3. Multi-chip Synchronization And Offset Circuit
Multiple chips are synchronized in a master/slave configuration. The M/S control pin is high for the
master chip and is low for the slave chip. The master chip drives the bi-directional DC, CV, FIZ, and FOZ
pins as outputs. The slave chips use the pins as inputs. The multi-chip mode control signal selects between
the internal filter controls and the external ones.
The master chip sends the 12 delay control bits (DC) and the control valid strobe (CV) to the slave
chips. The slave chips accept the DC and CV signals, add a delay offset to them and output the delay control
and control valid strobes to the resampler filter.
The FIZ and FOZ flags are used to lock the FIFOs in the slave chips to the master chip’s FIFO. The
FOZ and FIZ flags go high each time the fifo read or write address counters on the master chip go to zero.
These flags clear the read or write counters on the slave chips. FOZ controls the read counters, FIZ controls
the write counters.
2.7 OUTPUT FIFO
The 16 sample FIFO is used to smooth the output interface between data being generated
synchronous to the input clock and data being output synchronous to the output clock. If the interpolation
ratio is correct, then the FIFO would only need to be one or two samples deep. Since the ratio can not be
exact, the FIFO has been expanded to 16 words to allow a +/- 8 sample buffer. The +/- 8 sample buffer
prevents the FIFO from overflowing or underflowing while the RLL circuit (or an external adaption loop)
adapts to variations in the output clock.
GRAYCHIP,INC.
-6-
JULY 22, 1996
This document contains information which may be changed at any time without notice