GC3011 Datasheet, PDF (15/35 Pages) Texas Instruments – DIGITAL RESAMPLER

GC3011 DIGITAL RESAMPLER
DC[0:11]
CV
FOZ,FIZ
FRST
HF
FE
CKOUT
CK2X
DELAY CONTROL. Active high
The 12 bit delay control word is used in the master/slave mode to
lock the resampling ratio of multiple slave chips to a single master
chip. The master chip broadcasts its delay control word on these
pins. The slave chips accept the delay control word on these pins.
The direction of the pins is determined by the M/S pin. The DC
word is clocked out of and into the chips on the rising edge of the
input clock (CK).
CONTROL VALID. Active high
The control valid strobe is broadcast by the master chip in the
master/slave synchronization mode. The slave chips accept this
signal to identify when the delay controls are valid. The direction
of this pin is determined by the M/S pin.The CV strobe is clocked
out of and into the chips on the rising edge of the input clock (CK).
FIFO READ ZERO, FIFO WRITE ZERO. Active high
These controls are broadcast by the master chip in the
master/slave synchronization mode. The slave chips use these
signals to clear the FIFO input (FIZ) and FIFO output (FOZ)
counters. The FIZ signal is clocked in and out of the chips on the
rising edge of the input clock (CK). The FOZ signal is clocked in
and out of the chips on the rising edge of the output clock (OCK).
The direction of these pins are determined by the M/S pin.
FIFO RESET. Active high
This signal resets the FIFO to the half full state. This signal is
clocked into the chip on the rising edge of the input clock (CK) and
must be active for at least one input clock cycle.
HALF FULL. Active high
The FIFO half full flag. This signal is high when the FIFO is at least
half full, and zero otherwise. This signal is clocked out on the rising
edge of the input clock (CK)
FIFO ERROR. Active high
The FIFO full or empty flag. This signal is high when the FIFO is
either full or empty. If the FIFO is full, it will remain full until the
output clock speeds up. If the FIFO is empty, it will remain empty
until the output clock slows down. The output data will be unknown
while this flag is high. The FRST pin can be used to force the FIFO
to the half full state when a FIFO error occurs by connecting FE to
FRST. This signal is clocked out on the rising edge of the input
clock (CK).
CLOCK OUTPUT. Active high
The resampled clock output. The chip generates a 50% (nominal)
duty cycle clock at the resampled data rate and outputs it on this
pin.
DOUBLE RATE CLOCK OUTPUT. Active high
This clock is output at twice the CKOUT clock rate, but not
exceeding the highest clock frequency rating of the chip. This
clock is useful when two chips are used in parallel to increase the
data output rate.
GRAYCHIP,INC.
- 15 -
JULY 22, 1996
This document contains information which may be changed at any time without notice