GC3011 Datasheet, PDF (14/35 Pages) Texas Instruments – DIGITAL RESAMPLER

GC3011 DIGITAL RESAMPLER
3.1 PIN DESCRIPTIONS
SIGNAL
DI[0:11]
CK
OCK
SI
EIN
EVAL
DO[0:11]
DVAL
SO
M/S
DESCRIPTION
INPUT DATA. Active high
The 12 bit two’s complement input samples. New samples are
clocked into the chip on the rising edge of the clock. The input data
rate is assumed to be equal to the clock rate.
INPUT CLOCK. Active high
The clock input to the chip. The input signals are clocked into the
chip on the rising edge of this clock.
OUTPUT CLOCK. Active high
The output signals are clocked out of the chip on the rising edge
of this clock.
SYNC IN. Active low
The sync input to the chip. All timers, accumulators, and control
counters are, or can be, synchronized to SI. This sync is clocked
into the chip on the rising edge of the input clock (CK).
ERROR IN. Active high
The external error input to the rate-lock-loop circuit. This signal is
sampled on the rising edge of the input clock (CK).
ERROR VALID. Active high
EVAL identifies when the error to the RLL is valid. The
rate-lock-loop circuit updates when EVAL is high. This signal is
sampled on the rising edge of the input clock (CK).
OUTPUT DATA. Active high
The resampled data are output as a 12 bit words on these pins.
The bits are clocked out on the rising edge of the output clock
(OCK).
DATA VALID. Programmable active high or low level
The data valid strobe. This strobe is used to identify the valid
output samples when the chip is operated in the synchronous I/O
mode (common I/O clock mode). This strobe is clocked out of the
chip on the rising edge of the clock (CK). This strobe is active for
the clock cycle just before DO changes. The high/low polarity of
the strobe is programmable. See Section 2.5 for details.
SYNC OUT. Active low
This signal is either a delayed version of the input sync SI, the
sync counter’s terminal count (TC), or a one-shot strobe. The SO
signal is clocked out of the chip on the rising edge of the output
clock (OCK).
MASTER/SLAVE CONTROL. High for master, low for slave
This pin determines if the chip is the master or slave in a multi-chip
synchronization mode. This pin should be pulled high for the
master chip and grounded for the slave chips.
GRAYCHIP,INC.
- 14 -
JULY 22, 1996
This document contains information which may be changed at any time without notice