GC3011 Datasheet, PDF (1/35 Pages) Texas Instruments – DIGITAL RESAMPLER

SLWS130
GC3011 DIGITAL RESAMPLER
1.0 KEY FEATURES
• 80 million samples per second (MSPS) input rate
• Fractional rate change down to 1/4^th the input rate
• Synchronization logic to allow multi-chip complex
data operation.
• Multiple chips can be synchronized with fixed delay
offsets.
• Two chips allow rate changes up or down.
• 12 bit data I/O
• 32 bit rate control accumulator
• 16 sample output FIFO
• 15 tap linear phase interpolator
• 4096 interpolation steps
• 80% input passband (0 to 0.4F_CK)
• +/- 0.1 dB passband ripple
• Less than +/- 0.02 degrees rms phase jitter
• -73 dB image rejection
• 60 dB worst case NPR
• Adaptive rate change to lock the resampling
ratio to the output clock rate
• PLL/VCO to generate an output clock to
match the rate change
• Microprocessor interface for control, output,
and diagnostics
• Built in diagnostics
• 2W power at 50 MHz, 5 volts
• 520 mW at 30 MHz, 3.3 volts
• 100 pin QFP package
1.1 BLOCK DIAGRAM
A block diagram illustrating the major functions of the chip is shown in Figure 1
CV,FOZ,FIZ
DC[0:11] M/S FRST
DIN[0:11]
OCK
SI
CK
INTERPOLATION
RATIO
AND MODES
EIN
EVAL
12 bits
MULTI-CHIP
SYNC
AND OFFSET
12 bits
INTERPOLATION FILTER
15 TAPS
4096 STEPS
SYNC
CIRCUIT
TO ALL CIRCUITS
INTERPOLATION
RLL
ERROR
RESET IN
CLK IN
16 SAMPLE
FIFO
OUT
SI
CLK
OUT
ERROR
SO
OUTPUT
MODES
OUTPUT CLOCK
GENERATOR
(FIXED CLOCK MODE OR
PLL AND VCO)
A[0:3]
4 bits
C[0:8]
8 bits
R/W
CS
INTERPOLATION
RATIO
INTERPOLATION
MODES
OUTPUT
MODES
ERROR DATA BYPASS
OUTPUT MUX AND FORMAT
12 bits
FE HF DOUT[0:11] DVAL SO
CKOUT
CK2X
CVOUT
CVIN
Figure 1. GC3011 Block Diagram
-1-
JULY 22, 1996
This document contains information which may be changed at any time without notice