MSP430FG47X Datasheet, PDF (56/91 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
f_USCI
fmax,_BITCLK
PARAMETER
USCI input clock frequency
Maximum BITCLK clock frequency
(equals baudrate in MBaud) (see
Note 1)
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50%  10%
V_CC
MIN TYP MAX
f_SYSTEM
2.2V /3 V
2
t_
NOTES:
UART receive deglitch time
(see Note NO TAG)
2.2 V
3V
50 150
50 100
1. The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.
2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
UNIT
MHz
MHz
ns
ns
USCI (SPI master mode) (see Figure 31 and Figure 32)
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
SMCLK, ACLKm
Duty cycle = 50%  10%
V_CC
MIN
t_SU,MI
SOMI input data setup time
2.2 V
110
3V
75
t_HD,MI
SOMI input data hold time
2.2 V
0
3V
0
t_VALID,MO
SIMO output data valid time
UCLK edge to SIMO valid, C_L = 20 pF
2.2 V
3V
NOTE:
f_UCxCLK
=
1
2t_LO∕HI
with
t_LO∕HI
≥
max(t_{VALID,MO(USCI)}
+
t_{SU,SI(Slave),}
t_SU,MI(USCI)
+
t ) _{VALID,SO(Slave)} .
For the slave’s parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} refer to the SPI parameters of the attached slave.
MAX
f_SYSTEM
30
20
UNIT
MHz
ns
ns
ns
ns
ns
ns
USCI (SPI slave mode) (see Figure 33 and Figure 34)
t_STE,LEAD
PARAMETER
STE lead time
STE low to clock
TEST CONDITIONS
V_CC
2.2 V/3 V
MIN TYP
50
t_STE,LAG
STE lag time
Last clock to STE high
2.2 V/3 V
10
t_STE,ACC
STE access time
STE low to SOMI data out
2.2 V/3 V
50
t_STE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V/3 V
50
t_SU,SI
SIMO input data setup time
2.2 V
20
3V
15
t_HD,SI
SIMO input data hold time
2.2 V
10
3V
10
t_VALID,SO
SOMI output data valid time
UCLK edge to SOMI valid,
C_L = 20 pF
2.2 V
3V
75
50
NOTE:
f_UCxCLK
=
1
2t_LO∕HI
with
t_LO∕HI
≥
max(t_{VALID,MO(Master)}
+
t_SU,SI(USCI),
t_{SU,MI(Master)}
+
t ) _{VALID,SO(USCI)} .
For the master’s parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} refer to the SPI parameters of the attached master.
MAX UNIT
ns
ns
ns
ns
ns
ns
ns
ns
110 ns
75 ns
56
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