CC3200_15 Datasheet, PDF (55/71 Pages) Texas Instruments – CC3200 SimpleLink™ Wi-Fi® and Internet-of-Things Solution, a Single-Chip Wireless MCU

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CC3200
SWAS032F – JULY 2013 – REVISED FEBRUARY 2015
Start Address
0x4000 7000
0x4000 C000
0x4000 D000
0x4002 0000
0x4002 0800
0x4003 0000
0x4003 1000
0x4003 2000
0x4003 3000
0x400F 7000
0x400F E000
0x400F F000
0x4200 0000
0x4401 C000
0x4402 0000
0x4402 1000
0x4402 5000
0x4402 6000
0x4402 D000
0x4402 E000
0x4402 F000
0x4403 0000
0x4403 0000
0x4403 5000
0x4403 7000
0x4403 9000
0xE000 0000
0xE000 1000
0xE000 2000
0xE000 E000
0xE004 0000
0xE004 1000
0xE004 2000
Table 5-6. Memory Map (continued)
End Address
0x4000 7FFF
0x4000 CFFF
0x4000 DFFF
0x400 07FF
0x4002 0FFF
0x4003 0FFF
0x4003 1FFF
0x4003 2FFF
0x4003 3FFF
0x400F 7FFF
0x400F EFFF
0x400F FFFF
0x43FF FFFF
0x4401 EFFF
0x4402 0FFF
0x4402 2FFF
0x4402 5FFF
0x4402 6FFF
0x4402 DFFF
0x4402 EFFF
0x4402 FFFF
0x4403 FFFF
0x4403 0FFF
0x4403 5FFF
0x4403 7FFF
0x4403 9FFF
0xE000 0FFF
0xE000 1FFF
0xE000 2FFF
0xE000 EFFF
0xE004 0FFF
0xE004 1FFF
0xE00F FFFF
Description
GPIO port A3
UART A0
UART A1
I²C A0 (Master)
I²C A0 (Slave)
General-purpose timer A0
General-purpose timer A1
General-purpose timer A2
General-purpose timer A3
Configuration registers
System control
µDMA
Bit band alias of 0x4000.0000 through 0x400F.FFFF
McASP
SSPI
GSPI
MCU reset clock manager
MCU configuration space
Global power, reset, and clock manager (GPRCM)
MCU shared configuration
Hibernate configuration
Crypto range (includes apertures for all crypto-related
blocks as follows)
DTHE registers and TCP checksum
MD5/SHA
AES
DES
Instrumentation trace Macrocell™
Data watchpoint and trace (DWT)
Flash patch and breakpoint (FPB)
Nested vectored interrupt controller (NVIC)
Trace port interface unit (TPIU)
Reserved for embedded trace macrocell (ETM)
Reserved
Comment
Used for external serial
flash
Used by application
processor
5.9 Boot Modes
5.9.1 Overview
The boot process of the application processor includes two phases. The first phase consists of
unrestricted access to all register space and configuration of the specific device setting. In the second
phase, the application processor executes user-specific code.
Figure 5-3 shows the bootloader flow chart.
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Detailed Description
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