CC3200_15 Datasheet, PDF (47/71 Pages) Texas Instruments – CC3200 SimpleLink™ Wi-Fi® and Internet-of-Things Solution, a Single-Chip Wireless MCU

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CC3200
SWAS032F – JULY 2013 – REVISED FEBRUARY 2015
Figure 4-21. Camera Parallel Port Timing Diagram
Table 4-20 lists the timing parameters for the camera parallel port.
Parameter Number
I2
I3
I4
I7
I8
I9
Table 4-20. Camera Parallel Port Timing Parameters
Parameter
Parameter Name
Min
pCLK
Clock frequency
T_clk
Clock period
t_LP
Clock low period
t_HT
Clock high period
D
Duty cycle
t_IS
RX data setup time
t_IH
RX data hold time
Max
2
1/pCLK
T_clk/2
T_clk/2
45 to 55
2
2
Unit
MHz
ns
ns
ns
%
ns
ns
4.11.4.8 UART
The CC3200 device includes two UARTs with the following features:
• Programmable baud-rate generator allowing speeds up to 3 Mbps
• Separate 16 x 8 TX and RX FIFOs to reduce CPU interrupt service loading
• Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Line-break generation and detection
• Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation and detection
– 1 or 2 stop-bit generation
• RTS and CTS hardware flow support
• Standard FIFO-level and End-of-Transmission interrupts
• Efficient transfers using μDMA
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO
level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed
FIFO level
• System clock is used to generate the baud clock.
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Specifications
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