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CC3200_15 Datasheet, PDF (45/71 Pages) Texas Instruments – CC3200 SimpleLink™ Wi-Fi® and Internet-of-Things Solution, a Single-Chip Wireless MCU
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CC3200
SWAS032F – JULY 2013 – REVISED FEBRUARY 2015
Table 4-17. I2C Timing Parameters(1)
Parameter Number
I2
I3
I4
I5
I6
I7
I8
Parameter
tLP
tSRT
tDH
tSFT
tHT
tDS
tSCSR
Parameter Name
Clock low period
SCL/SDA rise time
Data hold time
SCL/SDA fall time
Clock high time
Data setup time
Start condition setup
time
Min
See (2).
–
NA
–
See (2).
tLP/2
36
Max
-
See (3).
–
3
–
–
Unit
System clock
ns
ns
System clock
System clock
System clock
I9
tSCS
Stop condition setup
24
time
–
System clock
(1) All timing is with 6-mA drive and 20-pF load.
(2) This value depends on the value programmed in the clock period register of I2C. Maximum output frequency is the result of the minimal
value programmed in this register.
(3) Because I2C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on
the external signal capacitance and external pullup register value.
4.11.4.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and boundary
scan architecture for digital integrated circuits and provides a standardized serial interface to control the
associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the
IEEE Standard 1149.1,Test Access Port and Boundary- Scan Architecture.
Figure 4-19 shows the JTAG timing diagram.
J2
J3
J4
TCK
TMS
J7
J8
TMS Input Valid
J7
J8
TMS Input Valid
TDI
J11
J9
J10
TDI Input Valid
J9
J10
TDI Input Valid
J1
TDO
TDO Output Valid
TDO Output Valid
Figure 4-19. JTAG Timing
SWAS031-069
Table 4-18 lists the JTAG timing parameters.
Parameter Number
J1
J2
J3
J4
J7
J8
J9
J10
Parameter
fTCK
tTCK
tCL
tCH
tTMS_SU
tTMS_HO
tTDI_SU
tTDI_HO
Table 4-18. JTAG Timing Parameters
Parameter Name
Min
Clock frequency
Clock period
Clock low period
Clock high period
TMS setup time
1
TMS hold time
16
TDI setup time
1
TDI hold time
16
Max
15
1/fTCK
tTCK/2
tTCK/2
Unit
MHz
ns
ns
ns
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