CC3200_15 Datasheet, PDF (46/71 Pages) Texas Instruments – CC3200 SimpleLink™ Wi-Fi® and Internet-of-Things Solution, a Single-Chip Wireless MCU

CC3200
SWAS032F – JULY 2013 – REVISED FEBRUARY 2015
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Table 4-18. JTAG Timing Parameters (continued)
Parameter Number
Parameter
Parameter Name
Min
Max
Unit
J11
tTDO_HO
TDO hold time
15
4.11.4.6 ADC
Table 4-19 lists the ADC electrical specifications.
Table 4-19. ADC Electrical Specifications
Parameter
Description
Condition and Assumptions
Min
Typ
Nbits
Number of bits
12
INL
Integral nonlinearity
Worst-case deviation from
–2.5
histogram method over full scale
(not including first and last three
LSB levels)
DNL
Differential nonlinearity
Worst-case deviation of any step –1
from ideal
Input range
0
Driving source
impedance
FCLK
Clock rate
Successive approximation input
10
clock rate
Input capacitance
3.2
Number of channels
4
F_sample
F_input_max
Sampling rate of each ADC
Maximum input signal frequency
62.5
SINAD
I_active
Signal-to-noise and distortion
Active supply current
Input frequency dc to 300 Hz
and 1.4 V_pp sine wave input
Average for analog-to-digital
during conversion without
reference current
55
60
1.5
I_PD
Power-down supply current for Total for analog-to-digital when
1
core supply
not active (this must be the SoC
level test)
Absolute offset error
FCLK = 10 MHz
±2
Gain error
±2
Figure 4-20 shows the ADC clock timing diagram.
Max
Unit
Bits
2.5
LSB
4
LSB
1.4
V
100
Ω
MHz
pF
KSPS
31
kHz
dB
mA
µA
mV
%
Internal Ch
Repeats Every 16 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
ADC CLOCK
= 10 MHz
Sampling
4 cycles
SAR Conversion
16 cycles
EXT CHANNEL 0
Sampling
4 cycles
SAR Conversion
16 cycles
INTERNAL CHANNEL
Sampling
4 cycles
SAR Conversion
16 cycles
EXT CHANNEL 1
Sampling
4 cycles
SAR Conversion
16 cycles
INTERNAL CHANNEL
Figure 4-20. ADC Clock Timing
4.11.4.7 Camera Parallel Port
The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a
FIFO, and generates DMA requests. The camera parallel port supports 8 bits.
Figure 4-21 shows the timing diagram for the camera parallel port.
46
Specifications
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