CC3200_15 Datasheet, PDF (26/71 Pages) Texas Instruments – CC3200 SimpleLink™ Wi-Fi® and Internet-of-Things Solution, a Single-Chip Wireless MCU

CC3200
SWAS032F – JULY 2013 – REVISED FEBRUARY 2015
www.ti.com
3.2 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
Table 3-4 describes the use, drive strength, and default state of these pins at first-time power up and reset
(nRESET pulled low).
Table 3-4. Drive Strength and Reset States for Analog-Digital Multiplexed Pins
State after Configuration of
Pin
Board Level Configuration Default State at First Power Analog Switches (ACTIVE, Maximum Effective Drive
and Use
Up or Forced Reset
LPDS, and HIB Power
Strength (mA)
Modes)
29
Connected to the enable pin
of the RF switch (ANTSEL1).
Other use not recommended.
Analog is isolated. The digital
I/O cell is also isolated.
Determined by the I/O state,
as are other digital I/Os.
4
30
Connected to the enable pin
of the RF switch (ANTSEL2).
Other use not recommended.
Analog is isolated. The digital
I/O cell is also isolated.
Determined by the I/O state,
as are other digital I/Os.
4
VDD_ANA2 (pin 47) must be
45
shorted to the input supply
rail. Otherwise, the pin is
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
driven by the ANA2 DC-DC.
50
Generic I/O
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
The pin must have an
52
external pullup of 100 K to Analog is isolated. The digital Determined by the I/O state,
the supply rail and must be I/O cell is also isolated.
as are other digital I/Os.
4
used in output signals only.
53
Generic I/O
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
57
Analog signal (1.8 V
absolute, 1.46 V full scale)
ADC is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
58
Analog signal (1.8 V
absolute, 1.46 V full scale)
ADC is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
59
Analog signal (1.8 V
absolute, 1.46 V full scale)
ADC is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
60
Analog signal (1.8 V
absolute, 1.46 V full scale)
ADC is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
as are other digital I/Os.
4
3.3 Pad State After Application of Power To Chip But Prior To Reset Release
When a stable power is applied to the CC3200 chip for the first time or when supply voltage is restored to
the proper value following a prior period with supply voltage below 1.5 V, the level of the digital pads are
undefined in the period starting from the release of nRESET and until DIG_DCDC powers up. This period
is less than approximately 10 ms. During this period, pads can be internally pulled weakly in either
direction. If a certain set of pins are required to have a definite value during this pre-reset period, an
appropriate pullup or pulldown must be used at the board level. The recommended value of this external
pull is 2.7 KΩ.
26
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: CC3200
Copyright © 2013–2015, Texas Instruments Incorporated