SMJ320C6701 Datasheet, PDF (50/62 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP^{†‡§} (see Figure 31)
NO.
PARAMETER
’C6701-14
’C6701-16
MIN MAX
UNIT
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
3
15 ns
2 tc(CKRX)
3 tw(CKRX)
4 td(CKRH-FRV)
9 td(CKXH-FXV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
2P
ns
C – 1¶ C + 1¶ ns
–4
4 ns
–4
5
ns
*3
*16
Disable time, DX high impedance following last data bit from ^{CLKX int}
12 tdis(CKXH-DXHZ) _{CLKX high}
CLKX ext
*–3
*2
ns
*2
*9
13 td(CKXH-DXV)
Delay time, CLKX high to DX valid.
CLKX int
CLKX ext
–2
4
ns
3
16
14 td(FXH-DXV)
Delay time, FSX high to DX valid.
FSX int
ONLY applies when in data delay 0 (XDATDLY = 00b) mode. _{FSX ext}
*–2
*4
ns
*2
*10
† _{CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references}
of that signal are also inverted.
‡ _{Minimum delay times also represent minimum output hold times.}
§ _{P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.}
¶ _{C = H or L}
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
*This parameter is not tested.
50
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