SMJ320C6701 Datasheet, PDF (46/62 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles^†‡ (see Figure 27, Figure 28, Figure 29, and
Figure 30)
NO.
1 tsu(SEL-HSTBL)
2 th(HSTBL-SEL)
3 tw(HSTBL)
4 tw(HSTBH)
10 tsu(SEL-HASL)
11 th(HASL-SEL)
12 tsu(HDV-HSTBH)
13 th(HSTBH-HDV)
14 th(HRDYL-HSTBL)
Setup time, select signals§ valid before HSTROBE low
Hold time, select signals§ valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals§ valid before HAS low
Hold time, select signals§ valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
’C6701-14
’C6701-16
MIN MAX
4
2
*2P
*2P
4
2
3
2
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
*1
ns
18 tsu(HASL-HSTBL)
Setup time, HAS low before HSTROBE low
*2
ns
19 th(HSTBL-HASL)
Hold time, HAS low after HSTROBE low
*2
ns
*This parameter is not tested.
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency}
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
§ _{Select signals include: HCNTRL[1:0], HR/W, and HHWIL.}
switching characteristics during host-port interface cycles^†‡ (see Figure 27, Figure 28, Figure 29,
and Figure 30)
NO.
PARAMETER
’C6701-14
’C6701-16
MIN MAX
UNIT
5 td(HCS-HRDY)
6 td(HSTBL-HRDYH)
Delay time, HCS to HRDY¶
Delay time, HSTROBE low to HRDY high#
1 12
ns
1 12
ns
7 toh(HSTBL-HDLZ)
Output hold time, HD low impedance after HSTROBE low for an HPI read
*4
ns
8 td(HDV-HRDYL)
Delay time, HD valid to HRDY low
*P – 3 *P + 3 ns
9 toh(HSTBH-HDV)
Output hold time, HD valid after HSTROBE high
3 12
ns
15 td(HSTBH-HDHZ)
Delay time, HSTROBE high to HD high impedance
*3 *12
ns
16 td(HSTBL-HDV)
17 td(HSTBH-HRDYH)
Delay time, HSTROBE low to HD valid
Delay time, HSTROBE high to HRDY high||
3 12
ns
3 12
ns
*This parameter is not tested.
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency}
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
¶ _{HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy}
completing a previous HPID write or READ with autoincrement.
# _{This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the}
request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.
|| _{This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write}
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
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