SMJ320C6701 Datasheet, PDF (26/62 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
clock PLL (continued)
3.3V
PLLV
CLKMODE0
CLKMODE1
CLKIN
PLLFREQ3
PLLFREQ2
PLLFREQ1
(see Table 3)
PLLMULT
PLL
PLLCLK
CLKIN
LOOP FILTER
Internal to ’C6701
1
CPU
0
CLOCK
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.
B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only
power-supply sequencing
The 1.9-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core supply should be
powered up first, or at the same time as the I/O buffers supply. This is to ensure that the I/O buffers have valid
inputs from the core before the output buffers are powered up, thus preventing bus contention with other chips
on the board.
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