SMJ320C6701 Datasheet, PDF (49/62 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
MULTICHANNEL BUFFERED SERIAL PORT TIMING
SGUS030 – APRIL 2000
timing requirements for McBSP^†‡ (see Figure 31)
’C6701-14
NO.
’C6701-16
UNIT
MIN MAX
2 tc(CKRX)
3 tw(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low
CLKR/X ext
*2P
ns
CLKR/X ext *P – 1
ns
CLKR int
*13
ns
CLKR ext
4
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low
CLKR int
*7
ns
CLKR ext
4
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR int
10
ns
CLKR ext
1
8 th(CKRL-DRV) Hold time, DR valid after CLKR low
CLKR int
4
ns
CLKR ext
4
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low
CLKX int
*13
ns
CLKX ext
4
11 th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
*7
ns
CLKX ext
3
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.}
‡ _{CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references}
of that signal are also inverted.
*This parameter is not tested.
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