TDC7200_15 Datasheet, PDF (5/50 Pages) Texas Instruments – TDC7200 Time-to-Digital Converter for Time-of-Flight Applications in LIDAR,Magnetostrictive and Flow Meters

www.ti.com
TDC7200
SNAS647C – FEBRUARY 2015 – REVISED AUGUST 2015
7 Specifications
7.1 Absolute Maximum Ratings
T_A = 25°C , VDD = 3.3V, GND = 0V (unless otherwise noted).^(1)(2)(3)
V_DD
V_I
V_{DIFF_IN}
V_{IN_GND_V}
DD
I_I
T_A
T_stg
Supply voltage
Terminal input voltage
|Voltage differential| between any two input terminals
|Voltage differential| between any input terminal and GND or VDD
Input current at any pin
Ambient temperature
Storage temperature
MIN
MAX
UNIT
–0.3
3.9
V
–0.3 V_DD+0.3
V
3.9
V
3.9
V
–5
5
mA
-40
125
°C
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3) All voltages are with respect to ground, unless otherwise specified.
7.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-
C101 ⁽²⁾
VALUE
±1000
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
7.3 Recommended Operating Conditions
T_A = 25°C , VDD = 3.3V, GND = 0V (unless otherwise noted).
V_DD
Supply voltage
V_I
Terminal voltage
V_IH
Voltage input high
V_IL
Voltage input low
F_{CALIB_CLK}
Frequency (Reference/Calibration Clock)
DUTY_CLOCK
Input clock duty cycle
TIMING REQUIREMENTS: Measurement Mode 1 ⁽¹⁾
T1_{STARTSTOP_Min} Minimum Time between Start and Stop Signal
T1_{STOPSTOP_Min} Minimum Time between 2 Stop Signals
T1_{STARTSTOP_Max} Maximum time bet. Start and Stop Signal
T1_{STOPSTOP_Max} Maximum time bet. Start and last Stop Signal
TIMING REQUIREMENTS: Measurement 2 ⁽¹⁾
T2_{STARTSTOP_Min} Minimum Time between Start and Stop Signal
T2_{STOPSTOP_Min} Minimum Time between 2 Stop Signals
T2_{STARTSTOP_Max} Maximum time bet. Start and Stop Signal
T2_{STOPSTOP_Max} Maximum. time bet. Start and last Stop Signal
TIMING REQUIREMENTS: ENABLE INPUT
T_REN
T_FEN
Rise Time for Enable Signal (20%-80%)
Fall Time for Enable Signal (20%-80%)
(1) Specified by design.
MIN
2
0
0.7 × VDD
0
1 ⁽¹⁾
NOM
8
50%
MAX
3.6
VDD
3.6
0.3 × VDD
16
UNIT
V
V
V
V
MHz
12
ns
67
ns
500
ns
500
ns
2×t_CLOCK
2×t_CLOCK
s
s
(2¹⁶-2)×t_CLOCK
s
(2¹⁶-2)×t_CLOCK
s
1 to 100
ns
1 to 100
ns
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: TDC7200
Submit Documentation Feedback
5