TDC7200_15 Datasheet, PDF (13/50 Pages) Texas Instruments – TDC7200 Time-to-Digital Converter for Time-of-Flight Applications in LIDAR,Magnetostrictive and Flow Meters

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TDC7200
SNAS647C – FEBRUARY 2015 – REVISED AUGUST 2015
Feature Description (continued)
8.3.2 CLOCK
TDC7200 needs an external reference clock connected to the CLOCK pin. The external CLOCK is used to
calibrate the internal time base accurately and therefore, the measurement accuracy is heavily dependent on the
external CLOCK accuracy. This reference clock is also used by all digital circuits inside the device; thus, CLOCK
has to be available and stable at all times when the device is enabled (ENABLE = HIGH).
Figure 15 shows the typical effect of the external CLOCK frequency on the measurement uncertainty. With a
reference clock of 1MHz, the standard deviation of a set of measurement results is approximately 243ps. As the
reference clock frequency is increased, the standard deviation (or measurement uncertainty) reduces. Therefore,
using a reference clock of 16MHz is recommended for optimal performance.
400
100
40
0 2 4 6 8 10 12 14 16 18
Clock Period (MHz)
D018
Figure 15. Standard Deviation vs. CLOCK
8.3.3 Counters
8.3.3.1 Coarse and Clock Counters Description
Time measurements by the TDC7200 rely on two counters: the Coarse Counter and the Clock Counter. The
Coarse Counter counts the number of times the ring oscillator (the TDC7200’s core time measurement
mechanism) wraps, which is used to generate the results in the TIME1 to TIME6 registers.
The Clock Counter counts the number of integer clock cycles between START and STOP events and is used in
Measurement Mode 2 only. The results for the Clock Counter are displayed in the CLOCK_COUNT1 to
CLOCK_COUNT5 registers.
8.3.3.2 Coarse and Clock Counters Overflow
Once the coarse counter value has reached the corresponding value of the Coarse Counter Overflow registers,
then its interrupt bit will be set to 1. In other words, if (TIMEn / 63) ≥ COARSE_CNTR_OVF, then
COARSE_CNTR_OVF_INT = 1 (this interrupt bit is located in the INT_STATUS register). COARSE_CNTR_OVF
= (COARSE_CNTR_OVF_H x 2⁸ + COARSE_CNTR_OVF_L), and TIMEn refers to the TIME1 to TIME6
registers.
Similarly, once the clock counter value has reached the corresponding value of the Clock Counter Overflow
registers, then its interrupt bit will be set to 1. In other words, if CLOCK_COUNTn > CLOCK_CNTR_OVF, then
CLOCK_CNTR_OVF_INT = 1 (this interrupt bit is located in the INT_STATUS register). CLOCK_CNTR_OVF =
(CLOCK_CNTR_OVF_H x 2⁸ + CLOCK_CNTR_OVF_L), and CLOCK_COUNTn refers to the CLOCK_COUNT1
to CLOCK_COUNT5 registers.
As soon as there is an overflow detected, the running measurement will be terminated immediately.
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