TDC7200_15 Datasheet, PDF (20/50 Pages) Texas Instruments – TDC7200 Time-to-Digital Converter for Time-of-Flight Applications in LIDAR,Magnetostrictive and Flow Meters

TDC7200
SNAS647C – FEBRUARY 2015 – REVISED AUGUST 2015
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Device Functional Modes (continued)
8.4.6 Measurement Sequence
The TDC7200 is a stopwatch IC that measures time between a START and multiple STOP events. The
measurement sequence of the TDC7200 is as follows:
1. After powering up the device, the EN pin needs to be low. There is one low to high transition required while
VDD is supplied for correct initialization of the device.
2. MCU software requests a new measurement to be initiated via the SPI™ interface.
3. After the start new measurement bit START_MEAS has been set in the CONFIG1 register, the TDC7200
generates a trigger signal on the TRIGG pin, which is typically used by the corresponding ultrasonic analog-
front-end (such as the TDC1000) as start trigger for a measurement (for example, transmit signal for the
ultrasonic burst)
4. Immediately after sending the trigger, the TDC7200 enables the START pin and waits to receive the START
pulse edge
5. After receiving a START, the TDC resets the TRIGG pin
6. The Clock counter is started after the next rising edge of the external clock signal (Measurement Mode 2).
The Clock Counter STOP Mask registers (CLOCK_CNTR_STOP_MASK_H and
CLOCK_CNTR_STOP_MASK_L) determine the length of the STOP mask window.
7. After reaching the Clock Counter STOP Mask value, the STOP pin waits to receive a single or multiple STOP
trigger signal from the analog-front-end (for example, detected echo signal of the ultrasonic burst signal)
8. After the last STOP trigger has been received, the TDC will signal to the MCU via interrupt (INTB pin) that
there are new measurement results waiting in the registers. START, STOP and TRIGG pin are disabled (in
Multi-Cycle Averaging Mode, the TDC will start the next cycle automatically by generating a new TRIGG
signal). Note: INTB must be utilized to determine TDC measurement completion; polling the INT_STATUS
register to determine measurement completion is NOT recommended as it will interfere with the TDC
measurement.
9. After the results are retrieved, the MCU can then start a new measurement with the same register settings.
This is done by just setting the START measurement bit via SPI. It is not required to drive the ENABLE pin
low between measurements.
10. The ENABLE pin can be taken low, if the time duration between measurements is long, and it is desired to
put the TDC7200 in its lowest power state. However, upon taking ENABLE high again, the device will come
up with its default register settings and will need to be configured via SPI.
8.4.7 Wait Times for TDC7200 Startup
The required wait time following the rising edge of the ENABLE pin of the TDC7200 is defined by three key
times, as shown in Figure 20. All three times relate to the startup of the TDC7200’s internal LDO, which is power
gated when the device is disabled for optimal power consumption. The first parameter, T1_{SPI_RDY}, is the time after
which the SPI interface is accessible. The second (T2_{LDO_SET1}) parameter and third (T3_{LDO_SET2}) parameter are
related to the performance of a measurement made while the internal LDO is settling. The LDO supplies the
TDC7200’s time measurement device, and a change in voltage on its supply during a measurement translates
directly to an inaccuracy. It is therefore recommended to wait until the LDO is settled before time measurement
begins.
The first time period relating to the measurement accuracy is T2_{LDO_SET1}, the LDO settling time 1. This is the time
after which the LDO has settled to within 0.3% of its final value. A 0.3% error translates to a worst case time
error (due to the LDO settling) of 0.3% x t_CLOCK, which is 375ps in the case of an 8MHz reference clock, or
187.5ps if a 16MHz clock is used. Finally, the time T3_{LDO_SET2} is the time after which the LDO has settled to its
final value. For best performance, it is recommended that a time measurement is not started before T3_{LDO_SET2} to
allow the LDO to fully settle. Typical times for T1_{SPI_RDY} is 100 µs, for T2_{LDO_SET1} is 300 µs, and for T3_{LDO_SET2} is
1.5 ms.
20
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