DS92LV16 Datasheet, PDF (5/25 Pages) National Semiconductor (TI) – 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

DS92LV16
www.ti.com
SNLS138H – JANUARY 2001 – REVISED APRIL 2013
DESERIALIZER SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_RCP Receiver out Clock t_RCP = t_TCP
Period
See Figure 10
RCLK
12.5
t_RDC
t_CLH
t_CHL
t_ROS
t_ROH
RCLK Duty Cycle
CMOS/TTL
Low-to-High
Transition Time
CMOS/TTL
High-to-Low
Transition Time
ROUT (0-9) Setup
Data to RCLK
ROUT (0-9) Hold
Data to RCLK
CL = 15 pF
See Figure 5
See Figure 12
RCLK
45
50
2
Rout(0-9),
LOCK,
RCLK
2
0.35*t_RCP
−0.35*t_RCP
0.5*t_RCP
−0.5*t_RCP
t_HZR HIGH to TRI-STATE
Delay
2.2
t_LZR LOW to TRI-STATE
Delay
See Figure 13
t_ZHR TRI-STATE to HIGH
Delay
Rout(0-9),
LOCK
2.2
2.3
t_ZLR TRI-STATE to LOW
Delay
2.9
t_DD
t_DSR1
t_DSR2
t_RNMI-R
t_RNMI-L
Deserializer Delay
Deserializer PLL
Lock Time from
PWRDWN (with
SYNCPAT)
Deserializer PLL
Lock time from
SYNCPAT
Ideal Deserializer
Noise Margin Right
See ⁽¹⁾
See Figure 17⁽²⁾
Ideal Deserializer See Figure 17⁽²⁾
Noise Margin Left
RCLK
35MHz
80 MHz
35MHz
80 MHz
35 MHz
80 MHz
35 MHz
80 MHz
1.75*t_RCP + 2 1.75*t_RCP + 5
3.7
1.9
1.5
0.9
−630
−230
Max
40
55
4
4
10
10
10
10
1.75*t_RCP + 7
10
4
5
2
+630
+230
Units
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
ps
ps
ps
ps
(1) Sync pattern is a fixed pattern with 8-bit of data high followed by 8-bit of data low.
(2) tRNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It
is a measurement in reference with the ideal bit position, please see Tl’s AN-1217(SNLA053) for detail.
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