DS92LV16 Datasheet, PDF (17/25 Pages) National Semiconductor (TI) – 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

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PIN DIAGRAM
DS92LV16
SNLS138H – JANUARY 2001 – REVISED APRIL 2013
Figure 22. DS92LV16TVHG (Top View)
Pin #
1
2
3
4
5, 10, 11, 15
6,9,12,16
7
8
13
Pin Name
RPWDN*
REN
CONFIG1
REFCLK
AVDD
AGND
RIN+
RIN-
DO+
PIN DESCRIPTIONS
I/O
Description
CMOS, I RPWDN* = Low will put the Receiver in low power, stand-by, mode.
Note: The Receiver PLL will lose lock.⁽¹⁾
CMOS, I REN = Low will disable the Receiver outputs. Receiver PLL remains
locked. (See LOCK pin description)⁽¹⁾
Configuration pin - strap or tie this pin to High with pull-up resistor. No-
connect or Low reserved for future use.
CMOS, I Frequency reference clock input for the receiver.
Analog Voltage Supply
Analog Ground
LVDS, I Receiver LVDS True Input
LVDS, I Receiver LVDS Inverting Input
LVDS, O Transmitter LVDS True Output
(1) Input defaults to "low" state when left open due to internal pull-device.
Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV16
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