DS92LV16 Datasheet, PDF (12/25 Pages) National Semiconductor (TI) – 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

DS92LV16
SNLS138H – JANUARY 2001 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
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The DS92LV16 combines a serializer and deserializer onto a single chip. The serializer accepts a 16-bit
LVCMOS or LVTTL data bus and transforms it into a BLVDS serial data stream with embedded clock
information. The deserializer then recovers the clock and data to deliver the resulting 16-bit wide words to the
output.
The device has a separate Transmit block and Receive block that can operate independent of each other. Each
has a power down control to enable efficient operation in various applications. For example, the transceiver can
operate as a standby in a redundant data path but still conserve power. The part can be configured as a
Serializer, Deserializer, or as a Full Duplex SER/DES.
The DS92LV16 serializer and deserializer blocks each has three operating states. They are the Initialization,
Data Transfer, and Resynchronization states. In addition, there are two passive states: Powerdown and TRI-
STATE.
The following sections describe each operation mode and passive state.
INITIALIZATION
Before the DS92LV16 sends or receives data, it must initialize the links to and from another DS92LV16.
Initialization refers to synchronizing the Serializer's and Deserializer's PLL's to local clocks. The local clocks must
be the same frequency or within a specified range if from different sources. After the Serializers synchronizes to
the local clocks, the Deserializers synchronize to the Serializers as the second and final initialization step.
Step 1: When V_CC is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE
and internal circuitry is disabled by on-chip power-on circuitry. When V_CC reaches V_CC OK (2.2V) the PLL in each
device begins locking to a local clock. For the Serializer, the local clock is the transmit clock, TCLK. For the
Deserializer, the local clock is applied to the REFCLK pin. A local on-board oscillator or other source provides
the specified clock input to the TCLK and REFCLK pin.
The Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the
Serializer block is now ready to send data or synchronization patterns. If the SYNC pin is high, then the Serializer
block generates and sends the synchronization patterns (sync-pattern).
The Deserializer output will remain TRI-STATE while its PLL locks to the REFCLK. Also, the Deserializer LOCK
output will remain high until its PLL locks to an incoming data or sync-pattern on the RIN pins.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. The Serializer that
is generating the stream to the Deserializer must send random (non-repetitive) data patterns or sync-patterns
during this step of the Initialization State. The Deserializer will lock onto sync-patterns within a specified amount
of time. The lock to random data depends on the data patterns and therefore, the lock time is unspecified.
In order to lock to the incoming LVDS data stream, the Deserializer identifies the rising clock edge in a sync-
pattern and after 150 clock cycles will synchronize. If the Deserializer is locking to a random data stream from
the Serializer, then it performs a series of operations to identify the rising clock edge and locks to it. Because this
locking procedure depends on the data pattern, it is not possible to specify how long it will take. At the point
where the Deserializer's PLL locks to the embedded clock, the LOCK pin goes low and valid data appears on the
output. Note that the LOCK signal is synchronous to valid data appearing on the outputs.
The user's application determines whether sync-pattern or lock to random data is the preferred method for
synchronization. If sync-patterns are preferred, the associated deserializers LOCK pin is a convenient way to
provide control of the SYNC pin.
DATA TRANSFER
After initialization, the DS92LV16 Serializer is able to transfer data to the Deserializer. The serial data stream
includes a start bit and stop bit appended by the serializer, which frame the sixteen data bits. The start bit is
always high and the stop bit is always low. The start and stop bits also function as clock bits embedded in the
serial stream.
The Serializer block accepts data from the DIN0-DIN15 parallel inputs. The TCLK signal latches the incoming
data on the rising edge. If the SYNC input is high for 6 TCLK cycles, the DS92LV16 does not latch data on the
DIN0-DIN15.
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