DS92LV16 Datasheet, PDF (16/25 Pages) National Semiconductor (TI) – 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

DS92LV16
SNLS138H – JANUARY 2001 – REVISED APRIL 2013
www.ti.com
DS92LV16 BLVDS SER/DES PAIR
General device specific guidance is given below. Exact guidance can not be given as it is dictated by other board
level /system level criteria. This includes the density of the board, power rails, power supply, and other integrated
circuit power supply needs.
DVDD = Digital section power supply
These pins supply the digital portion of the device and also receiver output buffers. The TX DVDD is less critical.
The RX DVDD requires more bypass to power the outputs under synchronous switching conditions. The receiver
DVDD pins power 4 outputs from each DVDD pin. An estimate of local capacitance required indicates a minimum
of 22nF is required. This is calculated by taking 4 times the maximum short current (4 X 70 = 280mA) multiplying
by the rise time of the part (4ns) and dividing by the maximum allowed droop in VDD (assume 50mV) yields
22.4nF. Rounding up to a standard value, 0.1uF is selected for each DVDD pin.
PVDD = PLL section power supply
The PVDD pin supplies the PLL circuit. Note that the DS92LV16 has two separate PLLs and supply pins. The
PLL(s) require clean power for the minimization of Jitter. A supply noise frequency in the 300kHZ to 1MHz range
can cause increased output jitter. Certain power supplies may have switching frequencies or high harmonic
content in this range. If this is the case, filtering of this noise spectrum may be required. A notch filter response is
best to provide a stable VDD, suppression of the noise band, and good high-frequency response (clock
fundamental). This may be accomplished with a pie filter (CRC or CLC). If employed, a separate pie filter is
recommended for each PLL to minimize drop in potential due to the series resistance. The pie filter should be
located close to the PVDD power pin. Separate power planes for the PVDD pins is typically not required.
AVDD = LVDS section power supply
The AVDD pin supplies the LVDS portion of the circuit. The DS92LV16 has four AVDD pins. Due to the nature of
the design, current draw is not excessive on these pins. A 0.1uF capacitor is sufficient for these pins. If space is
available it 0.01uF may be used in parallel with the 0.1uF capacitor for additional high frequency filtering.
GROUNDs
The AGND pin should be connected to the signal common in the cable for the return path of any common-mode
current. Most of the LVDS current will be odd-mode and return within the interconnect pair. A small amount of
current may be even-mode due to coupled noise, and driver imbalances. This current should return via a low
impedance known path.
A solid ground plane is recommended for both DVDD, PVDD or AVDD. Using a split plane may have potential
problem of ground loops, or difference in ground potential at various ground pins of the device.
16
Submit Documentation Feedback
Product Folder Links: DS92LV16
Copyright © 2001–2013, Texas Instruments Incorporated