DS92LV16 Datasheet, PDF (15/25 Pages) National Semiconductor (TI) – 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

DS92LV16
www.ti.com
SNLS138H – JANUARY 2001 – REVISED APRIL 2013
Input Failsafe
In the event that the Deserializer is disconnected from the Serializer, the failsafe circuitry is designed to reject
certain amount of noise from being interpreted as data or clock. The outputs will be tri-stated and the Deserializer
will lose lock.
Hot Insertion
All the LVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s)
makes contact first, then the VCC pin(s), then the I/O pins. When removing, the I/O pins should be unplugged
first, then the VCC, then the Ground.
PCB Layout and Power System Considerations
Circuit board layout and stack-up for the BLVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high-frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitic, especially proven effective at high frequencies above
approx 50MHz, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
It is a recommended practice to use two vias at each power pin as well as at all RF bypass capacitor terminals.
Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and
extending the effective frequency range of the bypass components. Locate RF capacitors as close as possible to
the supply pins, and use wide low impedance traces (not 50 Ohm traces). Surface mount capacitors are
recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller
value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the
50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and
ground pin straight to the power and ground plane, with the bypass capacitors connected to the plane with via on
both ends of the capacitor. Connecting power or ground pin to an external bypass capacitor will increase the
inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. User must pay attention to the resonance frequency of these
external bypass capacitors, usually in the range of 20-30MHz range. To provide effective bypassing, very often,
multiple capacitors are used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two via from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate CMOS (TTL) swings away from the LVDS
lines to prevent coupling from the CMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ohms
are typically recommended for LVDS interconnect. The closely-coupled lines help to ensure that coupled noise
will appear as common-mode and thus is rejected by the receivers. Also the tight coupled lines will radiate less.
Termination of the LVDS interconnect is required. For point-to-point applications termination should be located at
the load end. Nominal value is 100 Ohms to match the line's differential impedance. Place the resistor as close
to the receiver inputs as possible to minimize the resulting stub between the termination resistor and receiver.
Additional general guidance can be found in the LVDS Owner's Manual - available in PDF format from the Texas
Instruments web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml
Specific guidance for this device is provided next:
Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV16
Submit Documentation Feedback
15